AMD-762 Datasheet, PDF (107/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
Table 35. Initialization Pinstrapping (Continued)
Signal
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Type
Description
Three-State-Enable (For Test Only)
I
When pulled High, this pin enables board test mode when TEST# is asserted. Refer to
Chapter 3 for details of this test mode bit. The value of this pinstrap can be read in the
Configuration Status register (Dev 0:F0:0x88).
Inclk_Delay_Enable
When this pin is pulled High, forwarded clocks originating in the AMD-762™ system
I ^{controller are delayed 1/4 SysClk period to place their edge in the nominal center of the}
associated data. Certain SIP parameters are also adjusted. When pulled Low, the
forwarded clock edges are concurrent with the associated data transitions. The value of
this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88).
NAND_TreeEnable (for Test Only)
I
When this pin is pulled High, NAND tree test mode is enabled when TEST# is asserted. Refer
to Chapter 3 for details of this test mode bit. The value of this pinstrap can be read in the
Configuration Status register (Dev 0:F0:0x88).
CPU_ClkHist
This field selects the amount of hysteresis applied to the SysDataOutClk[3:0]# and
SysAddrOutClk# inputs for noise immunity. This field is encoded as follows:
I ^{00: No hysteresis}
01: Low hysteresis (preferred setting)
10: Medium hysteresis
11: Maximum hysteresis
TypeDet#
This pin functions as the AGP card type detect, used by the AGP I/O cells for impedance
compensation. The latched value of the TYPEDET# pin can also be read in the
I ^{Configuration Status register (Dev 0:F0:0x88).}
0: AGP card with 1.5-V referencing installed
1: AGP card with 3.3-V referencing installed
The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88).
CPU_Div 1
These pins define the clock multiplier for CPU 1, and are generated by the CPU. They are
used internally to create the frequency ID (FID) value, which is used in the generation of
SIP values sent to the AMD Athlon™ processor during initialization. The table below lists
the clock multipliers for each FID value.
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I
FID Value Multiplier FID Value Multiplier FID Value Multiplier FID Value Multiplier
0000
11.0
0100
5.0
1000
7.0
1100
9.0
0001
11.5
0101
5.5
1001
7.5
1101
9.5
0010
12.0
0110
6.0
1010
8.0
1110
10.0
0011
12.5
0111
6.5
1011
8.5
1111
10.5
The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88).
Chapter 7
Signal Descriptions
95