AMD-762 Datasheet, PDF (73/122 Pages) Advanced Micro Devices – System Controller

Case 1:
DQS
DQ
t_QHrd (max)
t_DQSQrd (min)
t_CKhi
t_CKlo
CK
ADDR/CMD
Read
DQS
t_DQSQ2CK
Case 2:
DQ
t_DQSQrd (max)
Note: Timing parameter symbols defined at controller interface, not at memory device interface (CAS latency = 2 shown unregistered).
Figure 19. Memory Read Cycle Timing