AMD-762 Datasheet, PDF (82/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
4.5.4
AMD Athlon™ Processor System Bus Timings
Table 27 shows the AMD Athlon processor system bus timings.
Table 27. AMD Athlon™ Processor System Bus/AMD-762™ System Controller AC Specification
Group Symbol
Parameter Description Minimum Nominal Maximum Units Notes
T_NB-SKEW-
SAMEEDGE
Output skew with respect to
the same clock edge
–
–
400
ps
1
T_NB-SKEW-
DIFFEDGE
Output skew with respect to a
different clock edge
–
–
1025
ps
1
T_NB-SU
Input Data Setup Time
500
–
–
ps 1, 2
T_NB-HD
Input Data Hold Time
800
–
–
ps 1, 2
T_RISE
Signal or Clock Rise Time
1
–
3
V/ns
T_FALL
Signal or Clock Fall Time
1
–
3
V/ns
C_DATA
Data Pin Capacitance
4
–
12
pF
C_INCLK
Input Clock Capacitance
4
–
12
pF
T_NB-SYSCLK-
TO-PAD
SYSCLK to Synchronous Signal
Output at Pad (CONNECT,
CLKFWDRST)
2400
–
4800
ps 4, 5
T_NB-SETUP-
Input Setup Time for
Synchronous Signal to SYSCLK
1500
–
TO-SYSCLK
(PROCRDY)
–
ps 4, 5
T_NB-HOLD-FRO
Input Hold Time for
Synchronous Signal to SYSCLK
1200
–
M-SYSCLK
(PROCRDY)
–
ps 4, 5
Notes:
* This table contains preliminary information, which is subject to change.
1. T_{NB-SKEW-SAMEEDGE} is the maximum skew within a clock-forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
T_{NB-SKEW-DIFFEDGE} is the maximum skew within a clock-forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
2. Input SU and HLD times are with respect to the appropriate clock forward group input clock.
3. The synchronous signals include PROCREADY, CONNECT, and CLKFWDRST.
4. This value is measured with respect to the rising edge of SYSCLKIN.
5. Test load = 25 pF.
70
Electrical Data
Chapter 4