AMD-762 Datasheet, PDF (72/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
DDR Read Timing
From Chip I/O
Buffers
DQ
Note: All information shown under DDR Read Timing is
preliminary. Figure 18 shows a block diagram of the
AMD-762 system controller DDR interface inputs, and
Figure 19 on page 61 shows memory read cycle timing.
CCLK
From PLL
set
DQ
DQS
PDL
Q
Memory Controller Logic
clr
set
DQ
Q
clr
.
Figure 18. AMD-762™ System Controller DDR Interface Inputs Conceptual Block Diagram
60
Electrical Data
Chapter 4