AMD-762 Datasheet, PDF (56/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
Table 5: AMD-762™ System Controller PCI NAND Tree Ordering
Order Input Pin Name Ball Order Input Pin Name Ball Order Input Pin Name Ball
1 AD[31]
2 REQ[6]#
3 GNT[5]#
4 REQ[5]#
5 GNT[6]#
6 REQ[4]#
7 AD[29]
8 AD[27]
9 REQ[3]#
10 AD[25]
11 GNT[4]#
12 CBE[3]#
13 AD[17]
14 REQ[2]#
15 REQ[1]#
16 AD[21]
17 REQ[0]#
18 CBE[2]#
19 AD[23]
20 AD[30]
21 IRDY#
AA-27
AH-17
AJ-18
AH-18
AG-17
AJ-19
AE-16
AF-17
AH-19
AE-17
AG-18
AF-18
AE-19
AH-20
AH-21
AF-19
AG-21
AF-20
AE-18
AH-22
AE-20
22 CBE[1]#
23 DEVSEL#
24 AD[28]
25 AD[26]
26 SERR#
27 AD[24]
28 AD[19]
29 AD[12]
30 AD[18]
31 AD[14]
32 AD[22]
33 AD[20]
34 AD[16]
35 TRDY#
36 AD[08]
37 STOP#
38 AD[10]
39 FRAME#
40 PAR
41 AD[07]
42 AD[15]
AF-22
AF-21
AJ-23
AH-23
AE-21
AG-23
AJ-24
AF-23
AJ-25
AE-22
AH-24
AG-24
AH-25
AJ-26
AF-24
AH-26
AE-23
AG-25
AJ-27
AE-24
AH-27
43 AD[05]
44 AD[13]
45 AD[03]
46 AD[01]
47 AD[11]
48 AD[00]
49 SBGNT#
50 AD[09]
51 WSC#
52 AD[06]
53 CBE[0]#
54 SBREQ#
55 AD[04]
56 AD[02]
AF-25
AG-27
AE-25
AF-26
AH-28
AE-26
AD-25
AG-28
AC-25
AF-27
AG-29
AE-27
AF-28
AF-29
3.3
44
PLL Bypass Test Mode
PLL bypass test mode provides a method to clock the
Northbridge core logic directly from an external source without
the need for the internal PLLs of the AMD-762 system
controller. This test mode is sometimes useful for motherboard
debug and is required in the three-state and NAND tree test
modes.
PLL bypass mode is entered by asserting the TEST# pin Low
and pulling the AD[09] pin High. There are two clocking
Test
Chapter 3