AMD-762 Datasheet, PDF (46/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
The S3 state is exited when the Southbridge detects an enabled
resume event. The Southbridge powers up all of the voltage
planes that are off during the S3 state by asserting PWRON#.
After all of the voltage planes in the system are within
specification, and all of the outputs of the system clock
generator are running within specification, PWRGD is asserted
to the Southbridge. The Southbridge then deasserts DCSTOP#
followed by deassertion of PCIRST# (the RESET# pin on the
AMD-762 system controller).
The AMD-762 system controller retains the state of the
memory controller configuration registers, which allows BIOS
to immediately access memory to retrieve and restore the
system context. There are two configuration bits that BIOS uses
to allow the AMD-762 system controller to differentiate
between S3 and all other states following an active to inactive
transition on the RESET# pin. Upon exiting the S3 sleep state,
BIOS writes the appropriate value to these bits, which causes
the AMD-762 system controller to exit self-refresh. The two
register bits (STR_Control) are in the DRAM Mode/Status
register (Dev 0:F0:0x58). Refer to the AMD-762™ System
Controller Software/BIOS Design Guide, order# 24416 for
detailed information on these bits.
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Functional Operation
Chapter 2