AMD-762 Datasheet, PDF (30/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
2.3.3
2.3.4
PCI Configuration
The AMD-762 system controller uses PCI configuration
mechanism #1 to select all of the options available for
interaction with the processor, DRAM, and the PCI bus. This
mechanism is defined in the PCI Local Bus Specification,
Revision 2.2. All configuration functions for the AMD-762
system controller are performed by using two I/O-mapped
configuration registers —IO_CNTRL (I/O address 0CF8h) and
IO_DATA (I/O address 0CFCh).
These two registers are used to access all the other internal
configuration registers of the AMD-762 system controller. The
AMD-762 system controller decodes accesses to these two I/O
addresses and handles them internally. A read to a nonexistent
configuration register returns a value of FFh. Accesses to all
other I/O addresses are forwarded to the PCI bus as regular I/O
cycles. Read and write cycles involving the AMD-762 system
controller configuration registers are only distinguished by the
address and command that is sent.
The AMD-762 system controller implements the following
configuration spaces:
n Device 0:Function 0 (host bridge configuration registers)
n Device 0:Function 1 (DDR I/O and PDL configuration)
n Device 1:Function 0 (PCI-PCI bridge, AGP configuration)
The Device 0:Function 1 space is disabled by default, and must
be enabled by writing to a specific bit in the PCI Control
register (Dev 0:F0:0x4C). The normal reserved PCI header
space (0x00-0x3F) in this function returns all 1s.
PCI Parity/ECC Errors
The AMD-762 system controller indicates that an ECC error
occurred on the memory bus by setting a bit in the status
register and optionally asserting the PCI SERR# signal. This
action results in the error being reported by the Southbridge.
The AMD-762 system controller does not check parity on the
PCI bus. The status bit (Dev 0:04h, bit 31) is always 0.
18
Functional Operation
Chapter 2