AMD-762 Datasheet, PDF (98/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
Table 34. Signal Descriptions (Continued)
Signal
REQ[6:0]#
REQ64#
ACK64#
RESET#
SERR#
STOP#
TRDY#
Type
Description
PCI Bus Request
As the PCI bus arbiter, the AMD-762™ system controller samples these device-specific bus
request signals to determine if another agent requires control of the PCI bus. In 66-MHz
I PCI mode only, REQ[2:0]# is used and all remaining request signals must be pulled up to
the inactive state.
These signals are sampled by the rising edge of every PCICLK. If active, the arbiter issues
the corresponding GNT[6:0]# when the bus is available.
Request 64
B _{This pin is used to signal that the master requests a 64-bit transfer. The AMD-762 system}
STS controller must assert this signal (Low) during reset (RESET# asserted Low) to signal
64-bit devices that they can operate in 64-bit mode.
B Acknowledge 64
STS This pin is used to signal that the agent is capable of completing a 64-bit transfer.
System Reset
Asserting RESET# resets the AMD-762 system controller and sets all register bits to their
default values (except memory controller registers as required for ACPI S3 support).
I
Bidirectional signals are three-stated and outputs are driven inactive. RESET# is driven by
the PCIRST# output of the AMD-768™ peripheral bus controller or AMD-766™ peripheral
bus controller. See “Pin States at Reset” on page 98.
This signal may be asynchronous to SYSCLK and PCICLK. It is synchronized internally,
therefore it must be active for a minimum of four PCICLK periods.
PCI System Error
O _{SERR# is used by the AMD-762 system controller to transfer GART errors, ECC errors, or}
OD AGP A_SERR# pin assertion errors to error reporting logic on the AMD-766 peripheral bus
controller.
PCI Stop
B _{As a target, the STOP# signal is asserted by the AMD-762 PCI target logic to initiate a}
STS target disconnect, ending the current transfer. As a master, the AMD-762 system controller
ends the current transfer when it samples the STOP# signal asserted.
PCI Target Ready
TRDY# is asserted by the AMD-762 system controller during accesses of DRAM by an
B ^{external bus master when read data is valid or when the target logic is ready to receive}
write data. This signal is sampled by the AMD-762 PCI master logic when the AMD-762
STS _{system controller is accessing an external PCI target.}
This pin is also optionally used in test modes as described in Table 36 on page 98, and in
Chapter 3.
86
Signal Descriptions
Chapter 7