AMD-762 Datasheet, PDF (41/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
5. After all queues are flushed, the AMD-762 system
controller’s power management logic requests the DRAM
controller to place the DRAM in self-refresh mode. The
DRAM controller initiates self-refresh, then acknowledges
to the power management logic.
• Self-refresh mode is initiated by generating an auto-
refresh cycle and deasserting the CKE pins.
6. The AMD-762 system controller issues a Stop Grant special
cycle on the PCI bus.
7. The Southbridge detects the Stop Grant special cycle on
the PCI bus and asserts the DCSTOP# signal.
8. The AMD-762 system controller samples DCSTOP# active
and gates off most of the internal clock trees. The DDR
DRAM address/command outputs are three-stated. The CKE
pins remain driven Low. The external clock sources and the
AMD-762 system controller PLLs continue to run.
• Note that the DDR DRAM clocks (CLKOUT[5:0],
CLKOUT[5:0]#) continue to run. This action is required
because the reset signal to the registered DIMMs is
connected to the AMD-762 system controller’s RESET# pin.
The RESET# pin is not asserted in the S1 state, thus the
clocks cannot be removed from the registered DIMMs.
Chapter 2
Functional Operation
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