AMD-762 Datasheet, PDF (100/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
Table 34. Signal Descriptions (Continued)
Signal
MAA[14:0] and
MAB[14:0]
CKEA and CKEB
MDAT[63:0]
MECC[7:0]
Type
Description
DDR Memory Address
The multiplexed row and column address bits MAA[14:0] and MAB[14:0] connect to the
system DDR SDRAMs. Two sets of memory addresses are provided to reduce signal
loading for motherboard designs with more than one DIMM slot. In an effort to reduce
switching noise on the DDR interface, the MAB bus is an inverted copy of the MAA bus,
O with the exception of the MA[10] bit that remains un-inverted on the MAB bus. The MAB
bus is not inverted from the MAA bus during the DDR device initialization phase.
The memory controller asserts or de-asserts these signals relative to CLKOUT at the
appropriate time in the memory access sequence. MAA[14:0] and MAB[14:0] are driven a
quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD time. See
Chapter 2, “Functional Operation” starting on page 7 for more information.
DDR Clock Enables
CKEA and CKEB are clock enable signals for the DDR DRAMs and are used for power
saving modes. They operate in parallel to drive greater loads than a single signal can
support.
O These control signals are driven inactive (negated) by RESET# or when the DDR devices
are placed in self refresh mode. The memory controller asserts or de-asserts these signals
relative to CLKOUT at the appropriate time in the memory access sequence. CKEA and
CKEB are driven a quarter of a cycle off from the CLKOUT rising edge to provide
additional HOLD time. See Chapter 2, “Functional Operation” beginning on page 7 for
more information.
DDR Memory Data
MDAT[63:0] connect to the DRAM data I/O. They are driven by the DDR DRAM during
reads and are driven by the AMD-762™ system controller during writes. During writes, the
AMD-762 system controller provides the clock-forwarded DQS[8:0] strobes centered
within the write data. The DQS strobes are used to capture the write data at the DDR
B DRAMs. (The DM pins provide additional strobes when accessing a x4 DIMM.) During
reads, the DDR DRAMs source the DQS strobes aligned with MDAT and are used within
the AMD-762 system controller to capture read data. (The DM pins are used to receive the
DQS signals from the DDR DRAMs when accessing a x4 DIMM.)
MDAT[63:0] are floated when neither the AMD-762 system controller nor the memory are
driving the bus.
DDR ECC
MECC[7:0] carry error correction codes for the eight bytes of data on MDAT[63:0]. These
signals are inputs to the AMD-762 system controller during DRAM read cycles and outputs
during DRAM write cycles. During writes, the AMD-762 system controller provides the
clock-forwarded DQS[8:0] strobes centered within the write data. The DQS strobes are
B
used to capture the ECC write data at the DDR DRAMs. (The DM pins provide additional
strobes when accessing a x4 DIMM.) During reads, the DDR DRAMs source the DQS
strobes aligned with MECC and are used within the AMD-762 system controller to capture
the ECC read data. (The DM pins are used to receive the DQS signals from the DDR
DRAMs when accessing a x4 DIMM.)
MECC[7:0] are floated when neither the AMD-762 system controller nor the memory are
driving the bus.
88
Signal Descriptions
Chapter 7