AMD-762 Datasheet, PDF (108/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
Table 35. Initialization Pinstrapping (Continued)
Signal
AD[15]
AD[14:12]
AD[11:10]
AD[9]
AD[8]
AD[7:5]
AD[4]
Type
Description
66-MHz PCI Mode
This bit is used to specify that the desired PCI clock speed is 66 MHz. This pin should be
I
pulled up if the motherboard supports the 66/33-MHz PCI speed option as described in
2.5 “System Clocking” on page 22. This should be pulled down for systems that support a
maximum PCI bus speed of 33 MHz.
The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88).
AGPClock_Mux[2:0] (For Test Only)
I
This bit field selects input to APLL clock mux for PLL test mode. Refer to Chapter 3 for
details of these bits. The value of this pinstrap can be read in the Configuration Status
register (Dev 0:F0:0x88).
Length 0
This bit field selects the CPU 0 physical AMD Athlon™ system bus length:
00: Short, non-slot A
01: Single slot A or “close”
I _{10: Far dual slot A}
11: Farthest possible slot A
For details of the bus length assumptions used in the bus timing calculations, see the
AMD Athlon™ System Bus Design Guide, order# 22666. The value of this pinstrap can be
read in the Configuration Status register (Dev 0:F0:0x88).
Bypass_PLLs (For Test Only)
I
If this pin is pulled High, PLL bypass mode is enabled when TEST# is asserted. Refer to
Chapter 3 for details of PLL bypass mode. The value of this pinstrap can be read in the
Configuration Status register (Dev 0:F0:0x88).
OutClk_Delay_Enable
When this pin is pulled High, forwarded clocks originating in the AMD Athlon processor
are delayed to the nominal center of the associated data. This control is provided by
I
adjusting SIP parameters. When pulled Low, the AMD Athlon processor forwarded clock
edges are concurrent with the associated data transitions.
Refer to the SIP mapping description in the AMD Athlon system bus specification (#21902)
for details. The value of this pinstrap can be read in the Configuration Status register (Dev
0:F0:0x88).
SysClock_Mux[2:0] (For Test Only)
I
This bit field selects input to SPLL clock mux for PLL test mode. Refer to Chapter 3 for
details of these bits. The value of this pinstrap can be read in the Configuration Status
register (Dev 0:F0:0x88).
CPU_Thresh
This pin functions as the AMD Athlon processor system bus threshold range select for
I ^{AMD Athlon processor system bus I/O cells. When Low, the AMD Athlon processor system}
bus inputs sense thresholds between 0.6 V and 1.0 V. When High, the inputs sense
thresholds between 1.0 V and 1.4 V. The value of this pinstrap can be read in the
Configuration Status register (Dev 0:F0:0x88).
96
Signal Descriptions
Chapter 7