AMD-762 Datasheet, PDF (24/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
System Clock
AMD-762™ System Controller
CLKOUTL[3],CLKOUTH[3]
CLKOUTL[2],CLKOUTH[2]
CLKOUTL[1],CLKOUTH[1]
CLKOUTL[0],CLKOUTH[0]
(MAA to even DIMMs,
MAB to odd DIMMs)
MAA[14:00], MAB[14:00]
MDAT[63:00], MECC[7:0]
DQS[8:0]
Differential
Clock Pairs
(1 per DIMM)
Figure 5.
DM[8:0]
RASA#, CASA#, WEA#
RASB#, CASB#, WEB#
CKEA
CKEB
CS[3:0]#
CS[7:4]#
(One pair of CS per DIMM)
DIMMs 0,1
AMD-762™ System Controller Connection to DDR DIMMs
DIMMs 2,3
2.2.1
DRAM Refresh
The AMD-762 system controller keeps track of when each of
CS[7:0] needs to be refreshed. Each CS is refreshed
independently. Refresh is only performed on rows that are
populated. A concurrent refresh cycle can be executed in
parallel with other read and write requests, if there is no CS
conflict and the command bus is free. Figure 6 on page 13
shows DRAM refresh timing.
Refresh rates are programmable by BIOS and can accommodate
various rates at 100-MHz or 133-MHz system bus speeds.
12
Functional Operation
Chapter 2