AMD-762 Datasheet, PDF (101/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
Table 34. Signal Descriptions (Continued)
Signal
Type
Description
CASA# and CASB#
DDR Column Address Strobes
CASA# and CASB# are column address strobe signals for the DDR DRAMs. They operate
in parallel to drive greater loads than a single signal can support. The CASx signal is 1 bit
of the 3-bit DDR DRAM command bus.
O _{These control signals are driven inactive (negated) by RESET#. The memory controller}
asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the
memory access sequence. CASA and CASB are driven a quarter of a cycle off from the
CLKOUT rising edge to provide additional HOLD time. See Chapter 2, “Functional
Operation” starting on page 7 for more information.
CLKOUT[5:0] and
CLKOUT[5:0]#
DDR Clock Outputs
O _{CLKOUT[5:0] and CLKOUT[5:0]# are differential clock pairs to the DDR DIMMs. The clock}
pairs can be individually disabled for unpopulated DIMM sockets.
RASA# and RASB#
DDR Row Address Strobes
RASA# and RASB# are row address strobe signals for the DDR DRAM. They operate in
parallel to drive greater loads than a single signal can support. The RASx signal is 1 bit of
the 3-bit DDR DRAM command bus.
O _{These control signals are driven inactive (negated) by RESET#. The memory controller}
asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the
memory access sequence. RASA and RASB are driven a quarter of a cycle off from the
CLKOUT rising edge to provide additional HOLD time. See Chapter 2, “Functional
Operation” starting on page 7 for more information.
WEA# and WEB#
DDR Memory Write Enables
WEA# and WEB# are write enable signals for the DDR DRAM. They operate in parallel to
drive greater loads than a single signal can support. The WEx signal is 1 bit of the 3-bit
DDR DRAM command bus.
O _{These control signals are driven inactive (negated) by RESET#. The memory controller}
asserts or de-asserts these signals relative to CLKOUT at the appropriate time in the
memory access sequence. WEA and WEB are driven a quarter of a cycle off from the
CLKOUT rising edge to provide additional HOLD time. See Chapter 2, “Functional
Operation” starting on page 7 for more information.
A_AD[31:00]
A_C/BE[3:0]#
AGPCLK
AGP/PCI Signals
AGP/APCI Address/Data Bus
B
These pins are the multiplexed address/data bus, sampled on the rising edge of AGPCLK.
The address is valid on A_AD[31:00] during the first clock when FRAME# is asserted. Write
TS data is valid on A_AD[31:00] when A_IRDY# is asserted and read data is valid when
A_TRDY# is asserted. Data transfers occur on A_AD[31:00] when both A_IRDY# and
A_TRDY# are asserted.
B ^{AGP/APCI Command/Byte Enables}
TS
During the address phase, these pins define the PCI command. During the data phase
these pins are used as byte enables.
AGP/APCI Clock
I _{AGPCLK receives a 66-MHz clock from the system clock generator. AGPCLK is used by the}
AMD-762™ system controller logic in the AGP clock domain.
Chapter 7
Signal Descriptions
89