AK2401 Datasheet, PDF (97/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
16.4. PCB Design
Below are board design guidelines confirmed by the conditions of our evaluation board and do not specify
layout pattern of customer's board or guarantee the characteristics.
- Connect the exposed pad in the center of the back to the low impedance analog ground. If the
exposed pad is not mounted, the operation may become unstable.
- The ADC is a 24-bit delta-sigma A/D converter. ADC operation clock is generated by dividing a
reference clock that is input to the TCXOIN pin by four. For this reason, since (TCXO/4) MHz and its
harmonic components leak to the input part of the LNA, selecting that frequency as the RF frequency
causes suppression of receiver sensitivity. Therefore, if customer’s RF frequency is equal to
multiplied by (TCXO/4) MHz, evaluate its performance with customer’s board. On our evaluation
board we confirm that the suppression of receiver sensitivity will be relaxed by paying attention to the
guidelines described below.
- Each VSS is not separated and connected to the same analog ground.
- Spurious characteristics are improved by short-circuiting the exposed pad and each VSS pin with the
TOP layer of the PCB.
- Power supply pins need to be careful not to go around LNA because ADVDD/DVDD is the main
spurious source. In addition to connecting a 100pF decoupling capacitor to each power supply pin,
10nF is added to LNAVDD and 1uF is added to ADVDD.
- Each power supply pin is wired in low impedance from LDO etc. without connecting ferrite beads in
series. Improvement of spurious characteristics is confirmed by connecting 1Ω in series only for
LNAVDD.
- Spurious characteristics degrade due to high frequency noise of AD_SCLK, AD_SDO, AD_FS pins.
Put 100Ω damping resistance in series. Fill the digital signal line in the inner layer.
- Connect decoupling capacitors, especially small capacitance ceramic capacitors as closely as
possible to AK2401.
- Use a balun connected to RFOUT_P, RFOUT_N pins depending on the frequency band. Because it
is an open collector pin, when using a balun without a center tap, it is necessary to supply the power
supply voltage separately through an inductor.
- For VREF1, VREF2 pins capacitor connected to ground, stabilize the internal circuit, connect the
specified value.
- All digital input pins must not be allowed to float.
017003093-E-00
97
2017/3