AK2401 Datasheet, PDF (14/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
Parameter
Symbol Min. Typ.
CSN setup time
SDATAIN setup time
SDATAIN hold time
SCLK high time
SCLK low time
CSN low hold time
CSN high hold time
t_CSS
40
t_DS
20
t_DH
20
t_WH
40
t_WL
40
t_CSLH
20
t_CSHH
40
SCLK to SDATA output delay time. 20pF load
t_DD
* Digital Input and output timings refer to a rising/falling signal of 0.5 VDD.
Max.
40
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
9.4. Serial Interface Timing for Programmable FIR Filter Coefficient Setting
By setting COEF_ST bit = “1” <Address 0x2D>, the AK2401 will enter coefficient setting mode for
programmable FIR filter from register writing mode. Write 16 bits coefficient data sequentially according
to the [CSN], [SCLK] and [SDATAI] timings shown below. Refer to “13.8.3. Programmable FIR Filter” for
details. AC timings such as clock speed and setup/hold timings are the same as the serial interface for
register access.
CSN
(Input)
SCLK
(Input)
SDATAI
(Input)
tCSS
tWH tWL
tCSHH
tCSLH
tDS tDH
D15 D14 D13 D12 D11
D4
D3
D2
D1
D0
Figure 6. Interface Timing for Programmable FIR Digital Filter Coefficient
9.5. Serial Interface Timing for ADC Data Readout
ADC data is readout via serial interface that is configured with the AD_FS, AD_SCLK and AD_SDO pins.
A 64-bit serial data is output from the AD_SDO pin in synchronization with a falling edge of the AD_SCLK
pin. The I channel serial data is output when the AD_FS pin = “H” and the Q channel serial data is output
when the AD_FS pin = “L” as 32-bit data for each channel. SDATAI signal does not include data and
output “0” on the first rising edge of the AD_SCLK. Following the “0” output, 24-bit receiving data after
ADC and digital filter processes is output in 2's complement format (MSB data will be fixed on the second
rising edge of AD_SCLK pin). The AD_SDO pin outputs internal status bits for 7clocks after the last data
of “D[0]”. Refer to “13.8.12 ADC P/S IF” for details.
The maximum clock frequency of the AD_SCLK output is 9.6MHz (when TCXO = 19.2MHZ). The
AD_SCLK signal frequency can be switched by setting the channel filter (DFIL_SEL[3:0] bits) <Address
0x22> and the sampling frequency (DFIL_SR[1:0] bits) <Address 0x22>. Refer to “13.8.11 Output
Sampling Rate” for details.
017003093-E-00
14
2017/3