AK2401 Datasheet, PDF (35/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.6. LOCAL BUFFER, LOCAL DIVIDER
13.6.1. LOCAL BUFFER
It is a buffer amplifier that amplifies the frequency of external local signal by multiplying by N (N=1, 2, 4,
8). The LOIN pin is internally matched to 50Ω. Input a signal to this pin via an AC coupling capacitor since
it is DC biased internally.
13.6.2. LOCAL DIVIDER
LOCAL DIVIDER consists of a local divider and a 90 degrees phase shifter. It converts a local signal that
is multiplied by the LOCAL BUFFER to a local frequency by dividing the signal by N (N=1, 2, 4, 8). It also
generates two local signals that have 90 degrees phase difference.
Operation frequency of the LOCAL DIVIDER will be different in receiving and transmitting modes. Refer
to “10.1.3 LOCAL BUFFER+LOCAL DIVIDER (RX)” and “10.2.2 LOCAL BUFFER+LOCAL
DIVIDER(TX)+DRIVER AMP” for details.
Analog characteristics of LOCAL DIVIDER such as orthogonality of I/Q phases, IIP2, LO leak and DC
offset are very different when N=1 comparing with other values (N=2, 4, 8). It is recommended to use
N=2, 4, 8 value for better characteristics of the LOCAL DIVIDER.
13.6.3. Phase Calibration
The AK2401 has a calibration function that corrects orthogonal difference of 90 degrees phase shifter.
There are two methods for this calibration. The one is using a calibration result of the factory default and
the other is using a value by register setting. It is controlled by TRIMREG_PH bit <Address0x14>.
Normally, TRIMREG_PH bit should be set to “0” and uses calibration result of the factory default.
 Using Calibration Result of the Factory Default
Set TRI0MREG_PH bit= “0”. The calibration result of the factory default is loaded by setting
PFUSE_RDST bit to “1” <Address0x41>. The factory default calibration result is measured in the
condition that is LOIN Input = 900MHz, 0dBm and DIVDEL [1:0] bit = “01” <Address0x12> (divide by 2).
 Using A Calibration Value by Register Settings
The orthogonality of the 90 degree phase shifter changes depending on local input frequency, Local
signal level, and Local HD2. A phase unbalance may be improved by using a value by register setting if
the local input signal condition is different from the factory default condition. Set TRIMREG_PH bit to “1”
and adjust PH_ADJ[4:0] bits for a register setting calibration value.
Figure 22 shows the effect of the second harmonic of the local signal on the orthogonality. (a) is a graph
showing the phase imbalance for the local second harmonic when using the factory calibration result. (b)
shows the output S/N ratio (Hum & Noise Ratio) after FM demodulation for phase imbalance. If the IQ
phase orthogonality is not sufficient, the S/N ratio will degrade. Therefore, it is recommended to keep the
phase imbalance to 1 degree or less.
(c) and (d) are graphs comparing the phase imbalance for the input signal power of the local signal
between the case where the second harmonic of the local signal is -50 dBc and the case of -20 dBc. (e)
and (f) are graphs comparing the phase imbalance for the input frequency of local signal between the
case where the second harmonic of the local signal is -50 dBc and the case of -20 dBc. As shown in the
graph, by minimizing the second harmonic of the local signal, the variation in phase imbalance for various
parameters is reduced.
017003093-E-00
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2017/3