AK2401 Datasheet, PDF (57/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.8.6. DC Offset Calibration
A DC offset calibration is performed in the analog and the digital receiving circuits independently. The DC
offset calibration for the analog receiving circuit is executed by the MIXER. In the digital receiving circuit,
DC offset calibrations are executed in the channel filter and the AGC that where the signal path is
bifurcated before the channel filter. Normally these calibrations are executed at the same time. However,
it is possible to execute these calibrations independently.
Refer to “12.3 DC Offset Calibration Sequence” for DC offset calibration sequence.
■ Analog Block (MIXER) DC Offset Calibration
DC offset calibration of the analog block is executed by the MIXER. The calibration starts by setting
OFSCAL1 bit to “1” <Address 0x17> and ends after 40µsec (CAL Time (1)). OFSCAL1 bit automatically
returns to “0” after the calibration is finished. The calibration result will be initialized by hardware or
software reset.
■ Digital Block (Channel Filter and AGC) DC Offset Calibration
DC calibrations for digital block are executed by the channel filter block and the AGC block. The
calibration starts by setting OFSCAL2 bit to “1” <Address 0x17>. In the calibration, moving averages of
the channel filter output and the AGC input are calculated and the calibration result is reduced from the
receiving data. The calibration time is shown in Table 9 and Table 10 (CAL Time (2)). OFSCAL2 bit
automatically returns to “0” after the calibration is finished.
The calibration result of the channel filter block can be readout from R_OFST_I[23:0] bits <Address 0x31
~ 0x33> and R_OFST_Q[23:0] bits <Address 0x34 ~ 0x36> when OFST_RSEL[1:0] bits are set to “00”
<Address 0x28>. And the calibration result of the AGC block can be readout from the same registers
when OFST_RSEL[1:0] bits are set to “11” <Address 0x28>. The calibration is calculated against each
PGA gain. Therefore the readback result will be the value for the setting gain at the time. The calibration
result will be initialized by hardware or software reset.
■ Digital Block (Channel Filter block only) DC Offset Calibration
A DC offset calibration for digital block is executed only at the cannel filter block by setting OFSCAL3 bit to
“1” <Address 0x17>. OFSCAL3 bit automatically returns to “0” after the calibration is finished.
■ Digital Block (AGC block only) DC Offset Calibration
DC offset calibrations are executed only at the AGC block by setting OFSCAL4 bit to “1” <Address 0x17>.
OFSCAL4 bit automatically returns to “0” after the calibration is finished.
OFSCAL3 bit and OFSCAL4 bit should be written independently when executing calibrations with these
bits. It is prohibited to set “1” to OFSCAL1 bit and OFSCAN2 bit simultaneously.
Normally, use OFSCAL1 and OFSCAL2 bits.
017003093-E-00
57
2017/3