AK2401 Datasheet, PDF (39/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.7.2. Frequency Setting
The frequency of the AK2401 is calculated as shown below.
FRAC
Frequency Setting= PFD
Frequency×
(INT+
)
MOD
PFD Frequency: Phase Comparison Frequency
INT: Settign for Integer Dividing Number (<Address0x07~0x08> Refer to “15.3 <0x07~0x08>INT”)
FRAC: Setting for Numerator of Fractional Divider (<Address0x01~0x03> Refer to “15.1
<0x01~0x03>FRAC”)
MOD: Setting for Denominator of Fractional Divider (<Address0x04~0x06> Refer to “15.2
<0x04~0x06>MOD”)
INT[11:0] bits must be set in the range of 35 ≤ INT ≤ 4091.
FRAC[17:0] bits must be set in the range of 0 ≤ FRAC ≤ (MOD-1).
MOD[17:0] bits must be set in the range of 2 ≤ MOD ≤ 262143 (dec). Since it is possible to set a fine
frequency with a larger value, normally set it to the maximum value 262143 (dec).
 Calculation Example of Setting Value
To achieve 910.0375MHz setting frequency with PFD Frequency = 4.8MHz,
Set values as below.
INT = 189
FRAC = 154965
MOD = 262143
Frequency Setting = 4.8 × (189 + 154965 / 262143) = 910.037504… [MHz]
13.7.3. Frequency Offset Adjustment
The AK2401 has an offset adjustable register that can tune the carrier frequency. The frequency is
recalculated by the timing mentioned later after setting OFST1[17:0] bits in <Address 0x0F~0x11> and
OFST2[17:0] bits in <Address 0x29~0x2B>. The recalculated frequency is used at the delta-sigma
modulator and N-Divider. When using the frequency offset function, be sure to set <Address 0x0C>
DSMON bit = "1".
OFST1 is assumed to use for AFC (Auto Frequency Control) and DFM (Digital Frequency Modulation).
OFST2 is necessary when using the real-time DC offset canceller (RDOC). Refer to “13.8.7 RDOC” for
the relationship between OFST2 and RDOC.
OFST1[17:0] bits or OFST2[17:0] bits are selected by RDOC_FM bit <Address 0x28> and the TX_PDN
pin settings as shown below.
RDOC_FM bit
0
0
1
1
TX_PDN pin
0
1
0
1
Offset Frequency
OFST1
OFST1
OFST2
OFST1
Selected offset frequency setting will be valid and the recalculation timings of the PLL synthesizer
frequency of each case are described below.
017003093-E-00
39
2017/3