AK2401 Datasheet, PDF (80/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
15.14. <0x19~0x1E>CH_DC OFST
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x19
OFST_I[23:16]
R/W
Initial value
0
0
0
0
0
0
0
0
0x1A
OFST_I[15:8]
R/W
Initial value
0
0
0
0
0
0
0
0
0x1B
OFST_I[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
0x1C
OFST_Q[23:16]
R/W
Initial value
0
0
0
0
0
0
0
0
0x1D
OFST_Q[15:8]
R/W
Initial value
0
0
0
0
0
0
0
0
0x1E
OFST_Q[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
OFST_I[23:0]: Ich DC Offset Compensation Value
OFST_Q[23:0]: Qch DC Offset Compensation Value
Set these bit to define DC offset compensation value arbitrarily for the channel filter block. This setting will
be valid instead of initial calibration value by setting OFS2REG bit = “1” <Address 0x17>.
The setting of <Address0x19> and <Address0x1A> will be valid when writing to the <Address0x1B>.
The setting of <Address0x1C> and <Address0x1D> will be valid when writing to the <Address0x1E>.
15.15. <0x1F~0x21, 0x47~048>AGC
Address
D7
D6
D5
D4
D3
0x1F
AGCTIM[2:0]
AGCHYS[1:0]
Initial value
0x20
Initial value
0
LNA_
AGC_OFF
1
1
LNA_
LGMODE
0
1
0
0
AGCMAX[2:0]
1
1
1
D2
AGC_
KEEPSEL
0
D1
AGC_
KEEPR
0
D0
AGCOFF
1
AGCTGT[2:0]
0
1
0
0x21
X
Initial value
FB_RDOC AGCKP_MODE[1:0]
X
0
0
0
AGCTRW[2:0]
0
1
1
0x47
X
X
LNA_TGT_H[5:0]
Initial value
1
0
0
0
1
0
0x48
X
X
LNA_TGT_L[5:0]
Initial value
1
0
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
Note that <Address0x47> and <Address0x48> are written in this document in a reverse order.
Refer to “13.8.8 AGC” and “13.8.9 AGC_KEEP” for AGC operation related to these settings above
017003093-E-00
80
2017/3