AK2401 Datasheet, PDF (90/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
15.23. <0x2E>PD
Address
D7
D6
D5
D4
D3
D2
D1
0x2E
Initial value
PD_
CLKBUF_N
0
PD_
LNA_N
0
PD_
RXR_N
0
PD_
TXR_N
0
PD_
SYNTH_N
0
PD_
ADC_N
0
PD_
DAC_N
0
Control each block power down. Refer to “13.1. Power Management” for details.
D0
R/W
PD_
REF_N _R/W
0
15.24. <0x2F~0x30>READ PGA
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x2F
R_LNA_
X
LGMODE
RPGA_I[5:0]
R
Initial value
0
0
0
0
0
0
0
0x30
X
X
RPGA_Q[5:0]
R
Initial value
0
0
0
0
0
0
R_LNA_LGMODE: LNA Gain Mode Readback (Readback Only)
Gain mode of the low noise amplifier is readback by writing the register addresses of this register. “0”
indicates Normal Gain Mode and “1” indicates Low Gain Mode. AGC calculation result is readback
when LNA_AGCOFF bit = “0”. The setting value of LNA_LGMODE bit will be readback when
LNA_AGCOFF bit = “1”.
RPGA_I[5:0]: Ich PGA Gain Readback (Readback Only)
RPGA_Q[5:0]: Qch PGA Gain Readback (Readback Only)
Setting gain of programmable gain amplifier is readback by writing the register addresses of these
settings above. AGC calculation result is readback when AGCOFF bit = “0” <Address 0x1E>. The
setting values of PGAGAIN_I[5:0] bits <Address 0x15> and PGAGAIN_Q[5:0] bits <Address 0x16> will
be readback when AGCOFF bit = “1”.
15.25. <0x31~0x36>READ OFST
Address
D7
D6
D5
D4
D3
D2
D1
0x31
R_OFST_I[23:16]
Initial value
0
0
0
0
0
0
0
0x32
R_OFST_I[15:8]
Initial value
0
0
0
0
0
0
0
0x33
R_OFST_I[7:0]
Initial value
0
0
0
0
0
0
0
0x34
R_OFST_Q[23:16]
Initial value
0
0
0
0
0
0
0
0x35
R_OFST_Q[15:8]
Initial value
0
0
0
0
0
0
0
0x36
R_OFST_Q[7:0]
Initial value
0
0
0
0
0
0
0
R_OFST_I[23:0]: Ich DC Offset Calibration Result (Readback Only)
R_OFST_Q[23:0]: Qch DC Offset Calibration Result (Readback Only)
DC offset value set by OFST_RSEL[1:0] bits <Address 0x28> are readback.
D0
R/W
R
0
R
0
R
0
R
0
R
0
R
0
017003093-E-00
90
2017/3