AK2401 Datasheet, PDF (43/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.7.5. Lock Detection
The AK2401 has a lock detection function to determine PLL lock/unlock state. The lock detection function
is enabled by setting LD bit = “0” <Address0x0C> and PLL lock detection signal is output from the LD pin
according to the internal logic. It is called digital lock detection.
The followings show the digital lock detection method. The LD pin outputs Low while the AK2401 is
unlock status after executing system reset. If the phase error that is lower than reference clock cycles is
detected “N” times continuously during unlock status, the AK2401 detects lock status and “H” signal is
output from the LD pin. The lock detection counter “N” is set by LD_LOCKCNT[7:0] bits <Address 0x3F>.
If the phase error that is more than “T” is detected for “N” times continuously during lock status, the
AK2401 detects unlock status and “L” signal is output from the LD pin. The unlock detection counter “N” is
set by LD_UNLOCKCNT[7:0] bits <Address 0x40>.
Setting values of LD_LOCKCNT[7:0] bits and LD_UNLOCKCNT[7:0] bits will be the count number “N” for
phase lock and unlock detection, respectively.
Do not set LD_LOCKCNT bits = “00000000” nor LD_UNLOCKCNT bits = “00000000”.
Timing chart of lock detection is shown in Figure 26.
Lock detection algorithm is shown in Figure 27.
Reference Clock
Phase Comparison Frequency
T/2
Dividing Clock of Oscillation Frequency
Phase Frequency Detector Output
Ignored since it
cannot be sampled ^Valid
LD Output
Ignored Ignored
Valid
Ignored
LD becomes “H” when sampling is
ignored (less or equal to T/2) for N times.
When R=1
Reference Clock
Phase Comparison Frequency
T
Dividing Clock of Oscillation Frequency
Phase Frequency Detector Output
Ignored since it
cannot be sampled
LD Output
Valid
Ignored since it
cannot be sampled
Valid
Ignored
LD becomes “H” when sampling is
ignored (less or equal to T) for N times.
When R > 1
Figure 26 Digital Lock Detect Operations
017003093-E-00
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