AK2401 Datasheet, PDF (75/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
15.6. <0x0C>SYNTH
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x0C
X
Initial value
FASTEN LFMODE
CPHIZ
X
0
0
0
DSMON
LD
X
R/W
0
0
FASTEN: Fast Lock Mode Enable Setting
This bit controls Fast Lock mode for frequency convergence of the PLL synthesizer. Refer to “13.7.4 Fast
Lock Function” for details.
0: Fast Lock Mode Disable
1: Fast Lock Mode Enable
LFMODE: PLL Synthesizer Operation Mode Setting
This bit switches the operation mode of the PLL synthesizer. Refer to “10.1.4 PLL SYNTHESIZER” for
the operation frequency of PLL synthesizer in each operation mode. The power consumption can be
reduced by setting low frequency mode.
0: High Frequency Mode (up to 2.4GHz)
1: Low Frequency Mode (up to 1.2GHz)
CPHIZ: TRI-STATE Charge Pump Output Setting
Charge pump output of the PLL synthesizer setting. Normally, CPHIZ bit should be set to “0”.
0: Normal Output
1: Tri-State
DSMON: Delta-sigma Modulator Setting
Set the operation of Delta-sigma modulator for integer dividing mode (FRAC=0).
The settings of OFST[17:0] bits <Address 0x0F~0x11> and OFST2[17:0] bits <Address
0x29~0x2B> are invalid when the Delta-sigma Modulator is not in operation. Normally, DSMON bit
should be set to “1”.
0: Do Not Operate Delta-sigma Modulator in integer dividing mode (FRAC=0)
1: Operate Delta-sigma Modulator in integer dividing mode (FRAC=0)
LD: Lock Detection Function Mode Setting
A function of the LD (lock detection) pin of the PLL synthesizer is set. Refer to “13.7.5. Lock Detection”
for the digital lock detection output when setting this bit to “0”. Refer to “13.8.7. RDOC Function” for the
local frequency.
0: Digital Lock Detection Output
1: Operation Status of Local Frequency Offset Control Function
15.7. <0x0D~0x0E>FAST TIME
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x0D
FAST_TIME[15:8]
R/W
Initial value
0
0
0
1
0
0
0
0
0x0E
FAST_TIME[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
FAST_TIME[15:0]: FAST Counter Time Setting
Set the valid period of fast lock mode for PLL synthesizer. The valid period is calculated as below. Do
not set FAST_TIME[15:0] bits =“0000000000000000”.
Valid period = Phase Frequency Detector Frequency Cycle × FAST_TIME[15:0] bit
This setting <Address0x0D> becomes valid after writing to the <Address0x0E>.
017003093-E-00
75
2017/3