AK2401 Datasheet, PDF (94/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
15.32. <0x4A>CH FILTER2
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x4A
X
X
X
X
X
TEST_1 DFIL_ACC
DFIL_
CLKG
R/W
Initial value
1
0
0
TEST_1 bit is a test bit. Write “1” to this bit.
DFIL_ACC : Digital Filter Accumulator Calculation Method Setting
Set the calculation method of the digital filter. Spurious of the operation frequency of the digital filter (such
as TCXO/4) will be changed. Normally, DFIL_ACC bit must be set to “0”.
0: PRBS (default)
1: Homogenized
DFIL_CLKG : Digital Filter Clock Gating Setting
Set ON/OFF of the clock gating of the digital filter. Spurious of the operation frequency of the digital filter
(such as TCXO/4) will be reduced. Normally, DFIL_CLKG bit must be set to “1”.
0: Clock Gating OFF (default)
1: Clock Gating ON (recommended)
15.33. <0x4B>STATUS
Address
D7
D6
0x4B
TEST_2 TEST_3
Initial value
0
0
D5
TEST_4
0
D4
TEST_5
0
D3
D2
D1
D0
R/W
LNALG_
STS
AGC_STS RSSI_STS
HPFFT_
STS
R/W
0
0
0
0
When writing “0” to this register, each status bit at ADC output serial interface is masked and outputs
“0”. When writing “1” to this register, each status bit will output status of corresponding block.
Refer to “13.8.12. ADC P/S IF” for details.
15.34. <0x5F>SOFT RESET
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x5F
SRST [7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
SRST[7:0]: Software Reset
Software reset is executed by writing to SRST[7:0] bits = “10101010”. This register will return to
“00000000” automatically when the software reset is completed. Refer to “9.2. System Reset” for
details.
017003093-E-00
94
2017/3