AK2401 Datasheet, PDF (26/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
Table 1 shows blocks that are powered on by the power management pins and register. The power
management pins is powered on by setting to “H” and the power management register is powered on by
setting “1”.
Table 1. Power-ON Management Block
Control
Method
Name
Power Management Block
Note
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
Power Up
Pin
SYNVDD pin
●
Pin
RX_PDN pin
●●●
●●
* 16
Receiving
Register
PD_LNA_N bit
PD_RXR_N bit
●
●
●●
PD_ADC_N bit
●
Transmitting
Pin
Register
TX_PDN pin
PD_TXR_N bit
PD_DAC_N bit
★
★ ★★
★ ★★
★
* 17
PD_SYNTH_N bit
◆◆
Other
Register ^{PD_CLKBUF_N bit}
◆
PD_REF_N bit
◆ * 18
Note:
* 16. There are no power control limitations for the TX_PDN pin polarity while the receiving block is in
operation. However, in order to enable OFST2 bit, it is necessary to control the TX_PDN pin. Refer
to “13.7.3. Frequency Offset Adjustment” for details.
* 17. The DAC block [4] can be excluded from TX_PDN pin powered down by setting <Address 0x13>
DACCNT bit = “0” (the default value is “1”). Then, control is performed only with PD_DAC_N bit.
* 18. The power management block [2] (MIXER, PGA, AAF) should be powered up when the power
management block [11] is powered up. In the same manner, the power management block [11] must
be powered down when the power management block [2] is powered down.
* ●, ★ and ◆ indicate blocks that are powered on.
Power management of receiving block is controlled by the RX_PDN pin, PD_LNA_N bit, PD_RXR_N bit
and PD_ADC_N bit. The register settings are ANDed. (e.g. It is necessary to set the RX_PDN pin = “H”
and PD_LNA_N bit = “1” to power up the LNA block [1].) In the same manner, the settings of the TX_PDN
pin, PD_TXR_N bit and PD_DAC_N bit are ANDed.
Power Management Sequence of Transmitting/Receiving Block is shown below.
 Power Management with The RX_PDN and The TX_PDN Pins
1. Power up the AK2401 according to “12.1 Power-up Sequence” section and put the device in the
state that register setting is available.
2. Fix the RX_PDN and TX_PDN pins to “L” and set power management registers of desired blocks
to “1”.
3. Set the RX_PDN or/and TX_PDN pins to “H” to start transmitting and receiving.
 Power Management with Registers
1. Power up the AK2401 according to “12.1 Power-up Sequence” section and put the device in the
state that register setting is available.
2. Fix the RX_PDN and TX_PDN pins to “H”. (It does not matter even if “H” at power-up.)
3. Set power management registers of desired blocks to “1” to start transmitting and receiving.
* The power management block [7] (LOCAL BUFFER) is controlled by ORed result of transmitting and
receiving blocks and PD_SYNTH_N bit.
[7] Power ON: (RX_PDN pin AND PD_RXR_N bit) OR (TX_PDN pin AND PD_TXR_N bit) OR
PD_SYNTH_N bit
* [8] LOCAL DIVIDER is controlled by ORed result of transmitting and receiving blocks. It will be in
operation by power up either transmitting or receiving block.
[8] Power ON: (RX_PDN pin AND PD_RXR_N bit) OR (TX_PDN pin AND PD_TXR_N bit)
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