AK2401 Datasheet, PDF (49/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
e.g.) When Input 12-bit 10TAP Coefficient
Coefficient Accuracy 12-bit
Dec
Bin
-37
1111 1101 1011
20
0000 0001 0100
351
0001 0101 1111
948
0011 1011 0100
1449
0101 1010 1001
1449
0101 1010 1001
948
0011 1011 0100
351
0001 0101 1111
20
0000 0001 0100
-37
1111 1101 1011
Input Value 16-bit
Bin
1111 1101 1011 0000
0000 0001 0100 0000
0001 0101 1111 0000
0011 1011 0100 0000
0101 1010 1001 0000
0101 1010 1001 0000
0011 1011 0100 0000
0001 0101 1111 0000
0000 0001 0100 0000
1111 1101 1011 0000
Hex
FDB0
0140
15F0
3B40
5A90
5A90
3B40
15F0
0140
FDB0
■ Bit Adjustment Block
After the accumulator, calculations for saturation process and bit shift can be applied by the
programmable FIR filter. PFIL_SAT[2:0] bits <Address0x23> control saturation process and
PFIL_SIFT[2:0] bits control bit shift operation. The output bit length is adjusted to 24-bit by saturation
process. Data process is executed in the order of saturation process and bit shifting.
Saturation Process
PFIL_SAT[2:0] bits <Address0x23> control the saturation process. The saturation process is applied
the accumulator 27-bit output (6.21). The output data will be adjusted to 24-bit since bit length is
changed after saturation process. If the bit length is over 24 bits, excess bits are rounded. If the bit
length is less than 24 bits, “0” data is added to the LSB to make data 24-bit.
PFIL_SAT
[2] [1] [0]
Saturation
Process
Output Bit Length
0
0
0
0-bit
(6.21) 27-bit
0
0
1
1-bit
(5.21) 26-bit
0
1
0
2-bit
(4.21) 25-bit
0
1
1
3-bit
(3.21) 24-bit
1
0
0
4-bit
(2.21) 23-bit
1
0
1
5-bit
(1.21) 22-bit
1
1
0
6-bit
(0.21) 21-bit
1
1
1
7-bit
(0.19) 20-bit
* 0-bit setting (PFIL_SEL[2:0] bits = “000”) indicates there is no change in output bit length. Even in
this case, the saturation process is executed.
Bit Shit
Bit shift setting is made by PFIL_SIFT[2:0] bits <Address0x23>. Bit shift is executed after the
saturation process and 24-bit adjustment. The bit length will not be changed after bit shift operation.
“0” data is added to the LSB for left shift, and “0” data is added to the MSB for right shift.
PFIL_SIFT
[2] [1] [0]
0
1
1
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
1
0
1
1
0
0
Bit Shift
Left 3-bit Shift
Left 2-bit Shift
Left 1-bit Shift
No Shift
Right 1-bit Shift
Right 2-bit Shift
Right 3-bit Shift
Do Not Set
017003093-E-00
49
2017/3