AK2401 Datasheet, PDF (22/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
11. Typical Performance Characteristics
Evaluation data assuming various wireless communication standards is prepared as an application note.
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12. Operation Sequence
12.1. Power-up Sequence
The AK2401 needs to be initialized by hardware reset (RSTN pin = “L”) upon power-up. The RSTN pin
must be held to “L” until VREF1 pin output is stabilized after power up each power supply (VDD1,
DACVDD, CPVDD and DVDD). The stabilization time of VREF1 pin depends on external capacitance of
the VREF1 pin and VREF2 pin. The maximum VREF1 pin stabilization time is 10msec when connecting a
100pF and 10μF capacitors in parallel to the VREF1 pin and 0.47μF capacitors to the VREF2 pin. (VDD1:
LNAVDD, DEMVDD, ADVDD, SYNVDD, LODVDD, LOVDD, RXVDD pins)
*AKM assumes no responsibility for the usage with a power-up sequence other than in this datasheet.
VDD1
DACVDD
CPVDD
DVDD
RSTN pin can set "H"
VREF1 pin
RSTN pin
Register accesible
10msec
Register
SPI
access
Figure 10. AK2401 Power-up Sequence
1. Set the RSTN pin to “L” and power up the power supplies (VDD1, DACVDD, CPVDD and DVDD).
DVDD must be powered up before or at the same time with SYNVDD. Except DVDD and SYNVDD,
power-up sequences between those power supplies are not critical. In addition, it is recommended to
start all the power supplies at the same time. Supply voltage to unused blocks and use registers for
powering down. The internal LOD will be powered up when SYNVDD is powered up.
2. The internal node (VREF1) will be risen with 10msec (max.) interval after power up the power
supplies (VDD1, DACVDD, CPVDD and DVDD).
3. Register write is enabled by bringing the RSTN pin = “H”.
4. Write Desired Register Values. According to 13.1 Power Management, PD_REF_N bit must be
started before PD_RXR_N bit. In addition, it is necessary to set phase calibration. Refer to 13.6.3
Phase Calibration.
The polarity of the TX_PDN and RX_PDN pins at power-up is not critical.
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