AK2401 Datasheet, PDF (51/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

Calculation Example 2) Maximum Coefficient Setting
[Coefficient Limits]
Bit Number
DC Gain
Max Coefficient
Total Coefficient
Absolute Maximum
Total Coefficient
PFIL_SAT[2:0]
PFIL_SIFT[2:0]
Bit
Times
Dec
Dec
Dec
Bin
Bin
16
16
32767
524288
1048576
001 (1-bit)
111 (1-bit Shift to Right)
[AK2401]
Location
Integer bit
65432
Fractional bit
▲••• Bit with Max Signal Level
1 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36
(1) Input
S DDDDDDDDDDDDDDDDDDDDD
↓
▲
15bits Extension for Multiplication
(2) Coefficient
S DDDDDDDDDDDDDDD
↓
▲
(3) Multiplier Output
↓
(4) Rounding Output
5bit Extension ^{S D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D}
for Accumulation
▲
S DDDDDDDDDDDDDDDDDDDDD
↓
▲
(5) Accumulator Output S D D D D D D D D D D D D D D D D D D D D D D D D D D
2 bits Deleted for 24-bit adjustment
↓
▲
(6) Adjust Part
SA S S D D D D D D D D D D D D D D D D D D D D D D D D
↓
▲
(7) Output
1biPtrSoacteusrsation
S
1bit Right Shift
S
D
D
D
▲
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
S _{••• Sign Bit} D _{••• Data Bit} SA _{••• Saturation Bit} D _{••• Delete Bit} 0 _{••• “0” Addition Bit} S _{••• Additional Sign Bit}
Figure 32. Programmable FIR Filter Calculation Example 2
A calculation example when input the maximum coefficient is shown here. In this example, a bit
adjustment is executed on the last step to make the total gain of digital filter -12dB (-19dBFS).
(1) Input bit length is (1.21). As shown in Figure 15, level diagram, the maximum input signal level of
programmable FIR filter is -13dBFS at full scale range. Therefore, the maximum signal is at -3
Fractional bit (▲) in Figure 32.
(2) Coefficient written by register setting. It has (1.15) bit length.
(3) Multiplication result of (1) and (2). Input signal is extended 15 bits according to the bit length of the
maximum coefficient.
(4) Round the data off to 21 bits to reduce the circuit size.
(5) Higher 5 bits are extended for accumulation. In this case, there is no excess bit since the maximum
value of the absolute total coefficient is input. The maximum signal bit is shifted 2 bits to the left
because the filter DC gain is 16 times larger (+24dB).
(6) Execute saturation process. In this example, 1-bit saturation process is executed. LSB 2 bits are
deleted to make the bit length to 26-bits after the saturation process. The data is shifted 1 bit to the
right and added “0” to the MSB as PFIL_SIFT[2:0] bits are set to “111”.
(7) At final output, the decimal point is shifted 1-bit to the left and the data becomes (1.23). It
expresses that the input signal is decreased by 6dB, and the digital filter total gain is -12dB
(-19dBFS).
017003093-E-00
51
2017/3