AK2401 Datasheet, PDF (38/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.7. PLL SYNTHESIZER
The delta-sigma fractional-N PLL synthesizer block integrates an 18-bit delta-sigma modulator, a divider
for reference clock, a phase frequency detector, a charge pump and an N-divider, composing a PLL with
an external loop filter and VCO. The PLL synthesizer has high frequency mode and low frequency mode
that define limits of operational frequency. LFMODE bit <Address0x0C> selects these modes. Power
consumption of the PLL synthesizer can be suppressed low by using low frequency mode.
13.7.1. CHARGE PUMP, LOOP FILTER
Two levels of charge pump current can be set to the AK2401. CPFINE[4:0] bits <Address 0x0A> set the
current for normal operation and CPFAST[4:0] bits <Address 0x0B> set the current for fast lock-up mode.
The PLL Fast Lockup mode is realized by switching these charge pump current by a timer for external
loop filter. The AK2401 integrates a switch for loop filter changing and operates the switch by the internal
timer.
Figure 23 shows the charge pump circuit and loop filter configuration example. The external loop filter
must be connected to the CP, SWIN and CPZ pins. The CPZ pin must be connected to the intermediate
node of the R2 resistor and the C2 capacitor even when not using the fast lock-up mode. In this case, the
R2 resistor should be connected to the CP pin and the C2 capacitor should be connected to the ground.
In fast lock-up mode, The R2 and R’2 resistors are connected in parallel internally by the internal switch.
The loop band and phase margin of fast lock-up mode should be calculated from the capacitances of R2
and R’2.
PHASE FREQUENCY
DETECTOR
UP
DOWN
Timer
LOOP FILTER
CP
C1 _R2'
R3
R2
C3
VCO
SWIN
C2
the switch of loop filter selector
On resistance : 150Ω
CPZ
Figure 23. Charge Pump and External Loop Filter Circuit Example
017003093-E-00
38
2017/3