AK2401 Datasheet, PDF (88/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
15.20. <0x29~0x2B>FREQ OFFSET2
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x29
X
X
X
X
X
X
OFST2[17:16]
R/W
Initial value
0
0
0x2A
OFST2[15:8]
R/W
Initial value
0
0
0
0
0
0
0
0
0x2B
OFST2[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
OFST2[17:0]: Frequency Offset Setting 2
Set frequency offset for PLL synthesizer. Setting value is in 2’s complement format and MSB is the sign
bit. Refer to “13.7.3. Frequency Offset Adjustment” for details of the frequency offset function. It is
recommended to set the offset frequency (OFST2 bits) to become 150Hz after divided by the local
divider. Set all “0” when not using the RDOC function. This setting is only valid when RDOC_FM bit = “1”
<Address0x28>. Refer to “13.8.7. RDOC Function” for details.
The setting of <Address0x29> and <Address0x2A> will be valid when writing to the <Address0x2B>.
15.21. <0x2C>RSSI
Address
D7
D6
D5
0x2C
X
X
X
Initial value
Refer to “13.8.10. RSSI” for setting details.
D4
D3
RSSI_LOW[1:0]
0
0
D2
D1
D0
R/W
RSSIAVE[2:0]
R/W
0
0
0
RSSILOW[1:0]: RSSI Compensation
Set a compensation value of RSSI code. The RSSI function subtracts the RSSI compensation value
from a detected signal level and outputs as RSSI code. The smaller the compensation value is the
smaller signal level can be detected.
RSSI_LOW
[1]
[0]
0
0
0
1
1
0
1
1
Compensation Value
[dB]
18 (default)
12
6
0
017003093-E-00
88
2017/3