AK2401 Datasheet, PDF (62/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
AGC relative registers are shown below.
PGA Control
<Address0x15> PGAGAIN_I[5:0] bits: PGA Ich Gain Setting
<Address0x16> PGAGAIN_Q[5:0] bits: PGA Qch Gain Setting
<Address0x1F> AGCHYS[1:0] bits: Hysteresis Width for Signal Power Convergence Level
<Address0x1F> AGCTIM[2:0] bits: Calculation/Detection Interval for Signal Power
<Address0x20> AGCTGT[2:0] bits: Target Value for Signal Power Convergence Level
<Address0x20> AGCMAX[2:0] bits: Maximum Gain Changing Amount in a Single AGC Operation
<Address0x21> AGCTRW[2:0] bits: Wait Time after Changing Gain
LNA Control
<Address0x20> LNA_AGCOFF bit: AGC ON/OFF setting of LNA
<Address0x20> LNA_LGMODE bit: Low Gain Mode Manual Setting of LNA
<Address0x47> LNA_TGT_H[5:0] bits: LNA Gain Switching Target (High)
<Address0x48> LNA_TGT_L[5:0] bits: LNA Gain Switching Target (Low)
PGA gain is set by PGAGAIN_I[5:0] bits and PGAGAIN_Q[5:0] bits manually when AGC_OFF bit =“1”.
When setting AGC_OFF bit = “1” → “0”, AGC operation will be executed using PGAGAIN_I[5:0] bits
setting as a default value. Ich and Qch gain settings will be the same during AGC operation.
Signal power is detected for every period set by AGCTIM bit after the wait time set by AGCTRW bit when
the AGC is in operation. Upper and lower limits of detection value are determined by AGCHYS bits
against signal power convergence target that is set by AGCTGT bits. AGC decreases the PGA gain if the
detected power is larger than the upper limit, and increases the PGA gain if the detected power is lower
than lower limit.
Adjustment amount of PGA gain is calculated by comparing detected power and target power to obtain
the closest detected power to the target. This calculation result of gain adjustment amount will be limited
by AGCMAX bits setting. After changing the PGA gain, next detection will be executed with an interval of
wait time set by AGCTRW bits and AGCTIM bits.
When detected power is in the limit range of (lower limit < detected power < upper limit), AGC stops
changing gain adjustment. After AGC operation is stopped, power detection is executed in every wait time
set by AGCTRW bits and AGCTIM bits. Therefore, if the detected power becomes out of the limit range
again, AGC resume the operation.
LNA has normal gain and low gain modes. When LNA_AGOFF bit = “0”, LNA gain is changed interlocked
with the PGA gain change. LNA gain switching is executed by comparing a correction gain (G_CORR) that is
calculated by AGCTGT bits with setting values of LNA_TGT_H[2:0] bits and LNA_TGT_L[5:0] bits.
G_CORR[dB] = G_N[dB] - TGT_CORR[dB]
AGCTGT
TGT_CORR
Unit
[2]
[1]
[0]
0
1
1
6
0
1
0
4 (default)
0
0
1
2
0
0
0
0
dB
1
1
1
-2
1
1
0
-4
1
0
1
-6
1
0
0
-8
017003093-E-00
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