AK2401 Datasheet, PDF (76/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
15.8. <0x0F~0x11>FREQ OFFSET1
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x0F
X
X
X
X
X
X
OFST1[17:16]
R/W
Initial value
0
0
0x10
OFST1[15:8]
R/W
Initial value
0
0
0
0
0
0
0
0
0x11
OFST1[7:0]
R/W
Initial value
0
0
0
0
0
0
0
0
OFST1[17:0]: Frequency Offset Setting 1
Set frequency offset for PLL synthesizer. Setting value is in 2’s complement format and MSB is the sign
bit. Refer to “13.7.3. Frequency Offset Adjustment” for details of the frequency offset function. Set all “0”
when not using the frequency offset function.
These settings <Address0x0F> and <Address0x10> will be valid after writing to the <Address0x11>.
15.9. <0x12>LOCAL
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x12
X
X
X
X
X
X
DIVSEL[1:0]
R/W
Initial value
0
1
DIVSEL[1:0]: Local Divider Setting
DIVSEL
[1]
[0]
0
0
0
1
1
0
1
1
Local Divider Setting
Not Divide
Divide by 2 (default)
Divide by 4
Divide by 8
15.10. <0x13>TX
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x13
DACCNT DACLV
TXOLV[1:0]
X
X
X
X
R/W
Initial value
1
0
0
0
DACCNT: DAC Power Down Control for TX_PDN Reset
This setting selects whether power down the DAC or not by power down control of the transmission
block by the TX_PDN pin. Refer to “13.1. Power Management” for details.
0: Do not control power down of the DAC by the TX_PDN pin
1: Control power down of the DAC by the TX_PDN pin
DACLV: DAC Operation Mode Setting
DAC operation mode is selected by DACLV bit. Refer to “10.2. Transmission Characteristics” for the
output level of the DAC in each operation mode. High level mode is only available when DACVDD = 4.5
~ 5.5V.
0: Low Level Mode (DACVDD=2.7 ~ 5.5V)
1: High Level Mode (DACVDD=4.5 ~ 5.5V)
017003093-E-00
76
2017/3