AK2401 Datasheet, PDF (53/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.8.4. High-Pass Filter
A high-pass filter will be enabled after FIR1 by setting HPFSEL bit to “1” <Address0x24>. This high-pass
filter cannot be used with the Real-time DC Offset Canceller (RDOC). Set DYOFSC[0] bit to “0” <Address
0x26> when using the high-pass filter.
The high-pass filter consists of first order IIR filter. HPF_FC[3:0] bits <Address 0x24> control the cutoff
frequency of the filter. The characteristics of the high-pass filter are shown in Table 4. The frequency
characteristics of the high-pass filter when using 19.2 MHz clock are shown in Figure 34.
Table 4. High-Pass Filter Frequency Characteristics
HPF_FC
Cutoff Frequency
Gain [dB]
[3] [2] [1] [0]
TCXO=19.2MHz TCXO=18.432MHz Unit
0 000
0.0
2.9 (default)
2.8 (default)
0 001
0.0
5.8
5.6
0 010
0.0
11.7
11.2
0 011
0.0
23.3
22.4
0 100
0.0
46.6
44.8
0 101
0.0
93.3
89.6
0 110
0.0
187
179
Hz
0 111
0.0
374
359
1 000
0.0
748
718
1 001
0.1
1504
1444
1 010
0.1
3031
2910
1 011
0.3
6159
5912
1 1XX
0.6
12714
12205
(X: Do not care)
017003093-E-00
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2017/3