AK2401 Datasheet, PDF (13/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
9.3. Serial Interface Timing for Register Access
Register write and read are executed via serial interface pins (CSN, SCLK, SDATAI and SDATAO pins).
A serial data input to the SDATAI pin consists of 1 bit Read/Write instruction, 7 bits address (MSB first,
A6~A0) and 8 bits data (MSB first, D7 ~ D0) in one frame (16 bits).
 Write Access (Write Command)
tCSS
CSN
(Input)
tWH tWL
tCSHH
tCSLH
SCLK
(Input)
SDATAI
(Input)
tDS tDH
R/W A6
A5
A1 A0 D7 D6
D1 D0
Figure 4. Interface Timing for Serial Register Write
 Read Access (Read Command)
tCSS
CSN
(Input)
tWH tWL
tDD
SCLK
(Input)
tCSHH
tCSLH
SDATAI
(Input)
R/W A6 A5
A1 A0
SDATAO
(Output)
D7 D6
D1 D0
Figure 5. Interface Timing for Serial Register Read
R/W: Instruction bit controls the operation that writes data to the AK2401 or reads out data from
the AK2401. When this bit is “0”, a write operation is executed. When this bit is “1”, a read
operation is executed.
A6 ~ A0: Register address to be accessed
D7 ~ D0: Write or Read data
(1) The CSN pin should be set to “H” when not accessing to the registers. The serial interfaces will
be activated by setting the CSN pin to “L”.
(2) During the CSN pin = “L”, register write is executed in synchronization to a rising edge of the
SCLK clock that is 16 cycles. A serial data is input to the SDATAI pin in the order of address and
data. The input data is latched on the 16th rising edge of the SCLK. The CSN pin must be set to
“H” every time data write is finished (note that input data will be invalid if the CSN pin becomes
“H” before 16th SCLK crock count).
(3) In read operation, instruction and address bits are received in synchronization to rising edges of
first 8 SCLK clocks and the data is read out in synchronization to falling edge of the last 8 SCLK
clocks. The CSN pin must be set to “H” every time data read is finished since a consecutive
reading is not supported.
017003093-E-00
13
2017/3