AK2401 Datasheet, PDF (28/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.3. Level Diagram
13.3.1. Level Diagram of Analog Receiving Circuit
Level diagram of analog receiving circuit when <Address 0x1F>AGC_OFF bit="0"(during AGC operation)
is shown in Figure 14. AGC operates so that the ADC input level becomes the set value of <Address
0x20> AGCTGT bit, and the dynamic range of the overall system is widened by changing the PGA gain.
The value of PGA Gain with respect to the LNA input level varies depending on the setting value of
AGCTGT bit, here, the level diagram at the time of AGCTGT bit ="011"(+6dBm) setting is stated.
The Low Gain Mode of LNA improves the distortion characteristics of the overall system by reducing the
input level to MIXER at the time of strong input. In the Low Gain Mode of LNA that is expected to be used
in exceeding IP1dB, the linearity of LNA self-confidence deteriorates compared to Normal Gain Mode.
Therefore, when LNA is switched from Normal Gain Mode to Low Gain Mode at strong input, the
distortion of the LNA output increases and the distortion of the MIXER output decreases. We expect that
the distortion component of 3 * RF frequency output from LNA by exceeding IP1dB of LNA will be
attenuated by external BPF between LNA and MIXER. For simplicity, it is assumed that there is no
insertion loss of the external BPF between LNA and MIXER.
AGCTGT bit="+6dBm"
OPTIONAL BPF
Ich/Qch Positive
From ANT/LPF
LNA
MIXER+PGA+AAF
to ADC
12@PGA Gain=20dB
20
0
-3
LNA Low Gain Mode
3@PGA Gain=11dB
-20
Ich/Qch Negative
6
-40 _-51
-36@PGA Gain=28dB
-60
LNA Normal Gain Mode
-64
-80
-100
-120
-121
-106@PGA Gain=28dB
Figure 14. Level Diagram of Analog Receiving Circuit
017003093-E-00
28
2017/3