AK2401 Datasheet, PDF (24/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
12.3. DC Offset Calibration Sequence
DC offset calibration starts by writing “1” to <Address 0x17> OFSCAL1 and OFSCAL2 bits (or OFSCAL3
and OFSCAL4 bits). When executing the calibration separately, it should be applied to the analog bock
(OFSCAL1) first and to the digital block (OFSCAL2) second. To stabilize the internal circuits, wait 1.5
msec before starting digital calibration after analog calibration. If OFSCAL1 and OFSCAL2 bits are set to
“1” simultaneously, analog calibration is executed first ant the digital calibration is executed next
automatically. Figure 12 shows the operation sequence of the DC offset calibration. Refer to 13.8.6 DC
Offset Calibration for details about CAL time(2).
PLL is locked or PD pin/bit ON, whichever comes later
PLL Synthesizer
Operation
Unlock
Lock
RX_PDN pin
<Address0x2E>
PD_RXR_N bit
PD_ADC_N bit
OFSCAL1 accesible
OFSCAL1
(Analog CAL)
OFSCAL2(or 3, 4)
(Digital CAL)
500μsec
OFSCAL2 accesible
1.5msec
CAL time (1) =40μsec
Figure 12. DC Offset Calibration Sequence
CAL time (2)
017003093-E-00
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