AK2401 Datasheet, PDF (45/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.8. Digital Receiving Circuit (ADC, DIGITAL FILTER, RSSI, AGC, ADC P/S IF)
A block diagram of digital receiving circuit is shown in Figure 28. An analog baseband signal that is
generated in the analog receiving circuit is over sampled by delta-sigma modulator by 64 times and
converted to digital data. Then the digital data is decimated with attenuating delta-sigma noise and input
to the cannel filter.
Signal level setting after the channel filter is stored to registers by RSSI function. It can be confirmed by
register readback function on SPI. A parallel-serial interface for the ADC outputs digital baseband signals.
The output sampling rate differs depending on a selected channel filter type.
Select either set of “High-pass Filter + Fast Track” or “DC Offset Calibration + RDOC” functions to cancel
DC offset that is superimposed to the baseband signals.
“DC offset + RDOC” functions should be selected normally. However, the RDOC function is not effective
when receiving a signal that is modulated by a method with amplitude variations like QPSK, π/4-shift
DQPSK and QAM. Select “High-pass Filter + Fast Track” functions for DC offset cancellation when
receiving such signals.
from
ΔΣ ADC
FIR1
Decimation
↓8
HPF
FIR2
Decimation
↓2
FIR3
Decimation
↓2
FIR4
Decimation
↓2
FIR5
Decimation
↓2
HPFSEL bit
To AGC Control
Channel Filter
F9
F4/F5/F6
/F7/F8
F1/F2/F3
Initial
DC Offset
Calibration
Real-time
DC Offset
Canceller
To ADC
P/S IF
RDOC bit
To RSSI
F0
↓2
Programmable
FIR Filter
Decimation Filter Part
Channel Filter Part
Figure 28. Digital Receiving Circuit
DC Offset Cancel Part
13.8.1. ADC
The ADC is a 24-bit delta-sigma A/D converter. ADC operation clock is generated by dividing a reference
clock that is input to the TCXOIN pin by four.
13.8.2. Digital Filter Frequency Characteristics
The channel filter characteristics can be selected from F0 to F9, or select a FIR filter that can be
programmed coefficient freely according to user preference. DFIL_SEL[3:0] bits in <Address 0x22>
select the filter. The programmable FIR filter can be selected by setting DFIL_PROG bit = “1”.
Two types of TCXO: 19.2 MHz and 18.432 MHz are recommended as standards characteristics for the
AK2401. Set DFIL_CLK bit = “0” <Address 0x22> when using 19.2MHz clock, and set DFIL_CLK bit = “1”
<Address 0x22> when using 18.432 MHz clock. FIR filter coefficients are adjusted to obtain same
attenuation characteristics at F0 ~ F9 filters with these two types of clocks. The filter characteristics are
shown in Table 3. The frequency characteristics are shown in Figure 29.
017003093-E-00
45
2017/3