AK2401 Datasheet, PDF (84/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
AGCTRW[2:0]: AGC Power Detection Wait Time
Set the wait time of power detection starts after PGA gain is changed in AGC operation.
AGCTRW
[2] [1] [0]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Wait Time
0.125
0.25
0.5
1 (default)
2
4
8
16
Unit
msec
15.16. <0x22>CH FILTER
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x22
Initial value
DFIL_SR[1:0]
0
0
DFIL_
PROG
DFIL_CLK
0
0
0
DFIL_SEL[3:0]
0
0
R/W
0
Refer to “13.8.2 Digital Filter Frequency Characteristics”, “13.8.3 Programmable FIR” and “13.8.11
Output Sampling Rate” for details of these settings.
DFIL_SR[1:0]: Output Sampling Rate
Select the sampling rate of digital filter outputs.
DFIL_PROG: Programmable FIR Filter Setting
Select normal channel filter or a programmable FIR Filter.
0: Use Normal Channel Filter set by DFIL_SEL[3:0] bits <Address 0x22>
1: Use a programmable FIR Filter set by <Address 0x2D> as Channel Filter
DFIL_CLK: Reference Clock Setting
Set reference clock that is input to the TCXOIN pin
0: 19.2MHz
1: 18.432MHz
DFIL_SEL[3:0]: Channel Filter Setting
Set Normal Channel Filter
15.17. <0x23>PROG FILTER
Address
D7
D6
D5
D4
D3
0x23
X
X
PFIL_SAT[2:0]
Initial value
0
0
0
D2
D1
D0
R/W
PFIL_SIFT[2:0]
R/W
0
0
0
PFIL_SAT[2:0]: Saturation Process Setting for Programmable FIR Filter Output
Set the number of bit for saturation process that is applied to the programmable FIR filter outputs.
PFIL_SIFT[2:0]: Bit Shift Setting for Programmable FIR Filter Output
Set the number of bit and sift direction (right or left) of bit shifting process that is applied to the
programmable FIR filter outputs.
017003093-E-00
84
2017/3