AK2401 Datasheet, PDF (23/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
12.2. Power-up Sequence of PLL Synthesizer
PD_SYNTH_N, PD_CLKBUF_N, PD_REF_N bits can set "1"
TCXOIN pin ^{Do not care}
<Address0x2E>
PD_SYNTH_N bit
PD_CLKBUF_N bit
PD_REF_N bit
Stable
500μsec
<0x08> accesible
PLL Synthesizer
Bias circuit
Power Down
Unstable
<0x01~0x07> can be accesss before
PLL Synthesizer Bias circuit is stable
<Address0x01~0x08>
INT, FARC, MOD bits
Register
access
Register
access
<0x08>
Stable
Register
access
PLL Synthesizer
Operation
Unlock
(Fast)
Lockup
Lock
Figure 11. Power-up Sequence of PLL Synthesizer
Write data to the registers in <Address 0x01 ~ 0x08>, synthesizer frequency settings will be valid when
writing to the last address “0x08” of the setting.
The synthesizer, clock buffer and reference circuits should be powered up when writing to the <Address
0x08>. Set PD_SYNTH_N, PD_CLKBUF_N and PD_REF_N bits = “1” in <Address 0x2E> to power on
these circuits with a stable TCXO input before setting synthesizer frequency. (Refer to “13.1. Power
Management” for details)
Wait 500µsec to stabilize the internal circuit after power on these circuits and execute register write to the
<Address 0x08> to set synthesizer frequency. Writing to the <Address 0x08> will be a trigger of frequency
change of the synthesizer. Fast Lock-up mode is enabled when the <Address 0x0C> FASTEN bit = “1”.
Refer to “13.7.4. Fast Lock Function” for details of the mode.
017003093-E-00
23
2017/3