AK2401 Datasheet, PDF (69/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.8.12. ADC P/S IF
The AK2401 outputs a data that is digitally processed by the ADC as a 64-bit serial signal. In the 64 bits,
I channel’s 24 bits and Q channel’s 24 bits are used as data area and the rest of 16 bits can be applied as
status bits for each function. Operational status of each function can be confirmed by the status bits.
Serial interface output of the ADC that includes status bits are shown in Figure 42. Normally, each status
bit is masked and outputs “0”. It will start outputting the status by writing “1” to the corresponding register
in the <Address0x4B>.
AD_FS
(Output)
Ich Data Output
Qch Data Output
AD_SCLK
(Output)
12 3
24 25 26 27
32 1 2 3
23 24 25 26
32
AD_SDO
(Output)
D23 D22
D1 D0 S13 S12
S7
D23 D22
D1 D0 S6 S5
S0
Figure 42. ADC Output Serial Interface Timing (Status Read)
S13~S10: Operational Status of Internal Circuit Flag (Control Register: TEST_2~TEST_5 bit)
S13 to S10 are test function for AKM USE. Set TEST_2 to TEST_5 bits = “0” to invalid.
S9: LNA Low Gain Mode Operation Flag (Control Register: LNALG_STS bit)
This flag becomes “1” while LNA is in operation in Low Gain Mode. This flag is valid in both AGC and
manual operations.
S8: AGC Gain Increment Flag (Control Register: AGC_STS bit)
This flag becomes “1” when PGA gain is increased during AGC operation. Flagging period is the same
as one cycle of the output sampling rate. The timing of flag can be selected by AGCKP_MODE[1:0] bits
<Address0x21>.
AGCKP_MODE[1:0] bits= “00”
This flag becomes “1” on the timing of a gain change in this setting.
AGCKP_MODE[1:0] bits= “01”
The flag becomes “1” on the timing of when the AGC_KEEP pin becomes “H” or AGC_KEEPR bit
becomes “1” if a gain change is recognized. The gain change will be reflected to LNA gain mode and
PGA gain setting on the timing when the AGC_KEEP pin become “L” or AGC_KEEPR bit become “0”
next time.
S7: AGC Gain Decrement Flag (Control Register: AGC_STS bit)
This flag becomes “1” when PGA gain is decreased during AGC operation. Flagging period and the
timing are the same as S8: AGC Gain Increment Flag.
S6~S1: RSSI Detection Value (Control Register: RSSI_STS bit)
Lower 6 bits of RSSI result that is read by setting RSSI bit <Address0x3A> are output in real-time. The
output range of lower 6 bits is from -127dBm to -95.5dBm(Typical, RSSI_LOW bit=”00”) with a
conversion to LNA input. All “1” is output after a saturation process if the output level exceeds -95.5
dBm of lower 6 bits. RSSI detection update timing is controlled by RSSIAVE bits <Address0x2C>
settings.
S0: HPF Fast Track Mode Transition Flag (Control Register: HPFFT_STS bit)
Valid when HPFSEL bit= “1” <Address0x24>.
This flag becomes “1” when HPF enters fast track mode. Flagging period is the same as one cycle of
the output sampling rate.
017003093-E-00
69
2017/3