AK2401 Datasheet, PDF (18/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
10.1.3. LOCAL BUFFER+LOCAL DIVIDER (RX)
Parameter
Min. Typ.
LOIN Input Sensitivity
-5
0
no div 300
2 div
50
Output Frequency Range
4 div
30
8 div
30
Max.
5
600
1200
600
300
Unit
dBm
MHz
MHz
MHz
MHz
Description
4 levels by
<Address0x12>
DIVSEL[1:0] bit
10.1.4. PLL SYNTHESIZER
BIAS2 pin=27kΩ
Parameter
Min. Typ. Max. Unit Description
N DIVIDER
100
Operating Frequency Range
100
2400
1200
MHz High Frequency Mode
MHz Low Frequency Mode
CLOCK BUFFER
TCXOIN Input Sensitivity
Operating Frequency Range
0.4
2
10
19.2 or
18.432
25
Vpp
* 12
MHz
PHASE FREQUENCY DETECTOR(PFD)
Phase Detector Frequency(F_PFD)
25
CHARGE PUMP(CP)
MHz
CP Current Adjust
22
27
33
kΩ Connect to BIAS2 pin
Maximum CP Current
Minimum CP Current
2400
75
I_CP TRI-STATE Leak Current
1
Sink/Source Current Mismatch * 13
10
I_CP vs V_CPO * 14
15
NOISE CHARACTERISTICS
μA _{32 levels by}
μA ^{<Address0x0A, 0x0B>}
nA
0.6 ≤ VCPO ≤ (CPVDD - 0.7)
(VCPO:CP pin Voltage)
%
VCPO = CPVDD/2
Ta = 25ºC
%
0.5 ≤ VCPO ≤ (CPVDD - 0.5)
Ta = 25ºC
Normalized Phase Noise
-210
dBc/Hz * 15
Notes:
* 12. In the case of using a TCXO other than 18.432MHz/19.2MHz, the cutoff frequency of the standard
channel filter change. Also note that the output sampling rate of the ADC is related to the TCXO
frequency. Refer to 13.8.2 Digital Filter Frequency Characteristics and 13.8.11 Output Sampling
Rate for datails.
* 13. Sink/Source Current Mismatch: [(|I_SINK|-|I_SOURCE|)/{(|I_SINK|+|I_SOURCE|)/2}]×100 [%]
* 14. I_CP vs V_CPO: [{1/2*(|I₁|-|I₂|)}/{1/2*(|I₁|+|I₂|)}]×100 [%]
* 15. It is calculated by the following formula with measuring in-band phase noise when PLL loop is locked.
TCXOIN=19.2MHz, F_PFD=19.2MHz
(PN_TOTAL = PN_SYNTH – 10 Log F_PFD – 20 Log N)
PN_TOTAL: Normalized Phase Noise, PN_SYNTH: In-band Phase Noise
017003093-E-00
18
2017/3