AK2401 Datasheet, PDF (60/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.8.8. AGC Function
Figure 35 shows block diagram of AGC function. In AGC operation, the total gain of I and Q channels is
detected by decimating the received signal to 1/8 after FIR1 filter, LNA gain mode setting value and PGA
gain are calculated to converge the signal to the target level. DC offset influences to the total power of I
and Q channels is removed by using a high-pass filter or by reducing the initial digital DC offset calibration
result.
A high-pass filter is used when HPF_SEL bit = “1” and calibration result is used when HPF_SEL bit = “0”
<Address 0x24>.
AGC function is enabled as shown below by setting AGCOFF bit <Address0x1F> and LNA_AGCOFF bit
<Address0x20>.
AGCOFF
LNA_AGCOFF
PGA
Description
LNA
0
0
AGC
AGC
0
1
AGC
Manual Setting
1
0
Manual Setting
PGA Manual Setting
1
1
Manual Setting
Manual Setting
Figure 36 shows AGC circuit flow chart. AGC operation starts by setting AGC_OFF bit = “0” (default “1”)
<Address 0x1F>. Following registers are AGC relative registers. AGC operation is executed according to
these settings. (Refer to “15.12 <0x15~0x16>PGA GAIN” and “15.15 <0x1F~0x21, 0x47~048>AGC” for
setting details)
LNA
PGA
PGA
AAF
AAF
ΔΣ
ADC
Decim-
ation
HPF
ΔΣ
ADC
Decim-
ation
Ich DC Offset
HPF
LNA Gain
Controler
Qch DC Offset
PGA Auto
Gain Controler
Figure 35. AGC Block Diagram
Power
Detect
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