AK2401 Datasheet, PDF (29/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.3.2. Level Diagram of Digital Receiving Circuit
Level diagram of digital receiving circuit is shown in Figure 15. The maximum input level of delta-sigma
block is 18dBm (=1.7 × VDD1[Vpp]), and -7dBFS at 24-bit full scale delta-sigma modulator. It will be
clipped if the input level exceeds this maximum level. Received signal is attenuated 6dB in the decimation
filter block. It will be output increasing by 6dB if using F0 ~ F9 filter for channel filter. Therefore the total
gain of the digital filter will be 0dB. When using the programmable filter for channel filter, coefficient and
bit adjustment should be executed in consideration of 6dB attenuation by the decimation filter. Refer to
“13.8.3. Programmable FIR Filter” for details.
RDOC (Real-time DC Offset Canceller) is optimized for a condition that the total gain of the digital filter is
0dB. It is recommended to design the DC gain of a programmable FIR filter to 6dB when using RDOC and
a programmable FIR filter for a channel filter.
Ich/Qch Positive
Ich/Qch Negative
24-bit
ΔΣ ADC
Decimation
Filter Part
Channel
Filter Part
DC Offset
Cancel
Part
ADC P/S IF
AD_SDO pin
Ich D[23:0]
AD_SDO pin
Qch D[23:0]
24-bit Full Scale(FS)
(25dBm@VDD1=3V)
-7dB FS
(18dBm@VDD1=3V)
Maximum Input
1.7×VDD1 differential
-13dB FS
(12dBm@VDD1=3V)
Figure 15. Level Diagram of Digital Receiving Circuit
017003093-E-00
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