AK2401 Datasheet, PDF (66/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
13.8.10. RSSI Function
The AK2401 has digital RSSI (Received Signal Strength Indicator) function. Figure 40 shows RSSI block
diagram. Input level is detected by the power detection circuit and LOG converted code is output. (When
DC offset calibration and RDOC functions are ON, RSSI processing is applied to the signal after these
processes.) Then, the data is averaged by the output sampling rate of when DFIL_SR[1:0] bits = “00”
<Address 0x22>. The number of sampling for averaging can be set by RSSIAVE[2:0] bits <Address
0x2C>.
The output code of the power detection circuit is a corresponding RSSI code that is added PGA gain
code. Then, a correction value set by RSSI_LOW[1:0] bits <Address 0x> is subtracted. In this case, PGA
gain code will be “0” at the maximum gain and the value of the code increases as the gain decrease.
Therefore, RSSI code decreases corresponding to the PGA input level even if the input level of power
detection circuit and ADC are kept stabled by AGC. The calculation result is stored to RSSI[7:0] bits
<Address 0x3A>.
The relationship of the Input level and the output code, when the gain of each block is a typical value and
normal power mode, is shown in the following expressions. Correct a gain difference of the output code
as needed if each block gain is not typical value or low power mode. The following expressions are
defined that the LNA is in normal gain mode; they do not cover the output correction of low gain mode.
Correct gain difference of the output code as needed when using low gain mode. Input/output
characteristics when RSSI_LOW bit “00” (18dB correction) is shown in Figure 41.
Output Code (dec) = 2 × (LNA Input Level [dBm] - RSSI_LOW bit Setting) + 290
LNA Input Level [dBm] = (Output Code (dec) - 290) ÷ 2 + RSSI_LOW bit Setting
(0.5dB resolution)
from DC Offset Cancel Part
<Address0x2C>
RSSI_LOW[1:0]
Ich Signal
Qch Signal
Power
Detecter
Average
4, 8, 16,
32, 64, 128
<Address0x3A>
RSSI[7:0]
<Address0x15>
PGAGAIN_I[5:0]
Figure 40. RSSI Block Diagram
017003093-E-00
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