AK2401 Datasheet, PDF (92/103 Pages) Asahi Kasei Microsystems – Direct Conversion Transceiver

[AK2401]
DC offset calibration result of the analog block that is executed by OFSCAL1 bit = “1” <Address 0x17>
can be readout. The calibration result will be stored at <Address 0x3B and 0x3C> if the calibration mode
is set to normal mode LPMODE bit = “0” <Address 0x14>. The calibration result will be stored at
<Address 0x3D and 0x3E> if the calibration mode is set to low power mode LPMODE bit = “1” <Address
0x14>.
By writing to these registers, a register setting value can be used instead of the calibration result. Note
that the calibration result will be over written in this case.
15.29. <0x3F~0x40>LDCNT
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x3F
LD_LOCKCNT[7:0]
R/W
Initial value
0
0
1
1
1
1
1
1
0x40
LD_UNLOCKCNT[7:0]
R/W
Initial value
0
0
1
1
1
1
1
1
LD_LOCKCNT[7:0]: Lock Detection Accuracy Setting
LD_UNLOCKCNT[7:0]: Unlock Detection Accuracy Setting
Set the number of detection time for digital lock/unlock detection mode. Refer to “13.7.5. Lock
Detection” for details.
*Do not set LD_LOCKCNT bit= “00000000” or LD_UNLOCKCNT bit= “00000000”.
15.30. <0x41~0x43>PHASE CAL
Address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0x41
X
X
X
X
X
X
PFUSE_
X
RDST
R/W
Initial value
0
0x42
X
X
PH_ADJ[5:0]
R/W
Initial value
1
0
0
0
0
0
0x43
X
X
R_PH_ADJ[5:0]
R
Initial value
0
0
0
0
0
0
PFUSE_RDST: Loading Trigger of I/Q Orthogonal Phase Calibration Value
When this bit is set to “1”, the I/Q orthogonal phase calibration value is loaded. It must be executed once
after hardware reset by the RSTN pin. This bit returns to “0” automatically, after finishing the load. Refer
to “13.6.3. Phase Calibration” for details.
* The loading value will not be reset by the software reset controlled by SRST[7:0] bits <Address 0x5F>.
017003093-E-00
92
2017/3