AK8850 Datasheet, PDF (95/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
PLL DAC SET REGISTER ( R / W ) [ SUB ADDRESS 0x47 ]
PLL control register.
Sub Address 0x47
bit 7
bit 6
PLLDACI7 PLLDACI6
1
0
bit 5
PLLDACI5
0
bit 4
bit 3
PLLDACI4 PLLDACI3
Default Value
0
0
bit 2
PLLDACI2
0
Default Value : 0x80
bit 1
bit 0
PLLDACI1 PLLDACI0
0
0
PLL DAC Set Register Definition
BIT Register Name
bit 0 PLLDACI0
PLL DAC INPUT bit
bit 7 PLLDACI7
R/W Definition
Adjust the External VCXO center frequency with
R/W _{this register. LSB is always disabled.}
Rev.0
95
2003/01