AK8850 Datasheet, PDF (65/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
7-4-21 OUTPUT INTERFACE
The AK8850 outputs decoded data in ITU-R BT.656 compatible interface formats, i.e.,
The sample number for each Line is guaranteed to be 858 / 864 ( 525 system / 625 system ) respectively.
Poor input quality or non Line-locked/Frame-locked PLL clocks may prevent ITU-R BT.656 compatible output. , In these
cases, the Input signal and Output data are correlated by the following 2 methods, selected by the [ OUTPUT FORMAT
REGISTER ].
( 1 ) Adjust using a Line-Drop / Repeat scheme ( number of Lines is not equal to 525 / 625, but number of samples is
guaranteed to be 858 / 864 ).
This process is performed when the final stage output buffer of the device either overflows or underflows.
( 2 ) Make 858 / 864 samples to be variable ( number of samples is not equal to 858 / 864, but number of Lines is
guaranteed to be 525 / 625 ).
Decoded data becomes ITU-R BT.656 compatible except for the last line of each Frame ( Line 3 in 525 system , Line 625
in 625 system ).i.e., typical 858 / 864 samples per each line is guaranteed other than at Line 3 / Line 625 ( 525 system /
625 system ).
The number of samples at Line 3 and Line 625 is un-determined since it is decided by relationdhip between the input
signal rate and the PLL-generated clock rate (it hovers around 858 / 864 samples ). In this processing mode, there is less
of a chance for buffer overflow or underflow since the buffer pointer is moved to the mid point of the buffer at the last line.
When either overflow or underflow occurs at the final stage buffer, a Line Drop / Repeat function is processed ( which can
occur when the input signal rate differs much from the PLL-generated clock rate ).
The DVALID pin output is “ low “ during the Active-Video period of the output data.
Relationship between HSYNC, DVALID and output data are shown below.
Video Signal
HSYNC
DVALID
CLK27MOUT
D[7:0]
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3
Active Video Start position
Normally, 123th/133th(525 system/625 system)pixel from 0H pixel
Y718 Cr359 Y719
Fine-tuning the Active-Video start position and a Y / C Delay amount to be output can be accomplished by programming
the [ OUTPUT FORMAT REGISTER ].
Rev.0
65
2003/01