AK8850 Datasheet, PDF (72/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
VERTICAL BLANKING LENGTH REGISTER ( R / W ) [ SUB ADDRESS 0x02 ]
Register to set VBI interval.
Sub Address 0x02
bit 7
bit 6
VBIDEC TRSVSEL
0
0
bit 5
HALFSU
0
bit 4
bit 3
VBIL4
VBIL3
Default Value
1
0
bit 2
VBIL2
1
Default Value : 0x14
bit 1
bit 0
VBIL1
VBIL0
0
0
Vertical Blanking Register Definition
BIT Register Name
R/W Definition
Set the VBI interval
bit 0
VBIL4
Vertical blanking
Length bit
Information
R/W
Default value is 20 (decimal)
-
i.e., Active video starts from Line-21
bit 4
VBIL0
The value of VBI[4:0] must be set more than 10.
Set the setup function for the first active line of
bit 5
HALFSU
Half Setup bit
R/W ^{the 2nd field.}
0 : 0.5H of 2nd field is not made setup process.
1 : 0.5H of 2nd field is made setup process.
Set the V-bit transition timing for EAV/SAV.
NTSC, 525 Component
TRSVSEL = 0 :
Line 1-9 / Line264-Line272 : V=1
bit 6 TRSVSEL ^{Time Reference Signal V Select} R/W ^{Other V=0}
bit
TRSVSEL = 1:
Line 1-19 / Line 264-Line282 V=1
Other V=0
625 Sytem : V-bit setting should reflect
TRSVSEL-bit setting
Output data while the VBI Interval.
0 : Y = 0x10
bit 7
VBIDEC
VBI Decode bit
R/W C = 0x80
1 : Y = input data(same as B/W process)
C = 0x80
For details, please refer to section 7-4-10 VERTICAL BLANKING INTERVAL.
Rev.0
72
2003/01