AK8850 Datasheet, PDF (38/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
* Clamp timing is set by [ FBCLPTMG 1 : FBCLPTMG 0 ]-bit ( bit-3 : bit-2 ).
[FBCLPTMG1:FBCLPTMG0]-bit
Clamp Pulse
00
Internal Synctip Clamp pulse
01
Internal Pedestal Clamp pulse
10
External clamp timing pulse input from EXTCLP pin.
11
Reserved
* Clamp timing and clamp level are summarized in the following table.
Internal Clamp timing pulse
Bit Set
286mV Sync signal
Synctip
Pedestal
300mV Sync signal
Synctip
Pedestal
[FBCLPTMG1:FBCLPTMG0]-bit
[CLPLVL1:CLPLVL0]-bit
Clamp
00
00
Clamp
01
01
Clamp
00
00
Clamp
01
10
External Clamp timing pulse
286mV Sync signal
300mV Sync signal
Synctip
Pedestal
Synctip
Pedestal
Clamp
10
Clamp
10
Clamp
10
Clamp
10
00
01
00
10
( 4 ) DIGITAL PEDESTAL CLAMP FUNCTION
This function clamps at the Pedestal position the Analog-clamped input signal by using digital signal processing. For
details, please refer to digital portion details.
Rev.0
38
2002/01