AK8850 Datasheet, PDF (7/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
3. Pin Functional Description
Pin
Number
2
3
4
Identification
SCL
SDA
SELA
6
FIELD
7
HSYNC
8
VSYNC
11
D7 (MSB)
12
D6
15
D5
16
D4
19
D3
20
D2
23
D1
24
D0 (LSB)
31
DVALID/VLOCK
34
FRAME1/CSYNC
35
FRAME0
36
HALFCLKOUT
39
CLK27MOUT
40
NSIG
41
NSTD
49
CLKINV
50
/RESET
52
CLK
54
EXTCLP
58
LLPF
59
LLPFC
60
FLPF
61
FLPFC
62
VREFOUT
63
IVCXO
64
IRefR1
65
IRefR2
66
VCOM
67
VRN
68
VRP
69
FBCAP3
[AK8850]
I/O
Description
I I2C bus Clock
I/O I2C bus Data (Open Collector )
I I2C bus address selector
FIELD Identify
O Low EVEN
High ODD
O HSYNC Timing output pin
O
VSYNC Timing output pin. (It is possible to output V_Blank Signal (VD) by
setting a register)
O Decoded data output pin (MSB)
O
O
O
O
Decoded data output pin
O
O
O Decoded data output pin (LSB)
O
Active Video Timing signal (720 Pixel)
It can also output VLOCK status by setting a register.
O When a standard signal is input, a color frame signal is output.
When a non-standard signal input, this pin outputs a timing signal that is
O toggled every 525/625 lines.
FRAME1 pin can output the CYSNC signal by setting a register.
O
When Rec.656 data is output, this signal identifies the signal as Y or C.
(This rate is about 13.5MHz)
O Output Timing of output data (About 27MHz)
O When No-signal is input this pin goes High.
O When Non-standard signal is input, this pin goes High.
I This pin decides the polarization of CLK27MOUT.
Reset Signal input pin. (Low Active)
I After Power up or power down mode, Reset signal should be Low at least
10msec.
I Input 27MHz Clock.
I/O External Clamp timing input pin.
O Connect Loop Filter for Line Lock clock.
O Connect Capacitors for Line Lock clock.
O Connect Loop Filter for Frame Lock clock.
O Connect Capacitors for Frame Lock clock.
O
Internal Voltage Reference output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
O
Control voltage output pin for the external VCXO.
Connect via a resistor to AVSS.
O
Terminate with 13kΩ resistor (0.1% accuracy) to AVSS.
This Register sets the reference current for the PLL Block.
O
Terminate with 4.7kΩ Register (0.1% accuracy) between AVSS.
This Register sets the internal reference current.
O
Internal common voltage for ADC output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
O
Internal negative voltage for ADC output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
O
Internal positive voltage for ADC output pin.
Terminate with 0.1uF or larger capacitor between AVSS.
O Terminate using a 0.033uF capacitor between AVSS. (for Clamp Level)
Rev.0
7
2002/01