AK8850 Datasheet, PDF (41/99 Pages) Asahi Kasei Microsystems – NTSC Digital Video Decoder

ASAHI KASEI
[AK8850]
* [ CLKMODE1 : CLKMODE0 ]-bit set
[CLKMODE1: CLKMODE0 ]
00
Fixed clock
01
Line-Locked Clock
10
Frame-Locked Clock
11
Auto Clock Mode
External Clock mode
Line Lock Clock mode
According to the input video signal quality, AK8850 works in
Fixed clock mode.
Frame Lock Clock mode
According to the input video signal quality, AK8850 works in
Fixed clock mode.
According to the Input video signal quality, Clock mode is
switched to the most suitable clock mode.(default)
The VCXO’s oscillating center frequency control voltage is adjusted by setting the DAC output current value [ PLL DAC
SET REGISTER ]. In Fixed Clock mode operation, the VCXO oscillating frequency is fixed by the value set here.
* [ PLL DAC SET REGISTER ]
bit 7
PLLDACI7
1
bit 6
PLLDACI6
0
bit 5
PLLDACI5
0
bit 4
PLLDACI4
0
bit 3
PLLDACI3
0
bit 2
PLLDACI2
0
The DAC’s upper 7 bits are valid. Adjustable DAC current value ranges are as follows.
bit 1
PLLDACI1
0
bit 0
Reserved
0
PLLDAC[7:1]
0000000
1111111
[uA] Typ.)
0
127
( 7-2-5 ) LOOP FILTER
The AK8850 requires external loop filters. Proper loop filters should be connected for the Line-Locked and the
Frame-Locked PLLs respectively. The optimum value of the loop filter constant varies with the VCXO gain [ ppm / V ]
characteristics.
C2
R1
C1
LLPF (For Line Lock)
FLPF (For Frame Lock
LLPFC ( For Line Lock)
FLPFC ( For Frame Lock)
An example of the loop filter constant for a 100 ppm/V VCXO is shown ( IVCXO output load resistor at 10 Kohm ).This loop
filter constant ( reference value ) is set by the [ PLL CONTROL REGISTER ] ( Sub address 0x46 ) [ LPGAUTO ]-bit
[LPGAUTO] - bit = 0 (Default)
[LPGAUTO]-bit = 1
R
C1
C2
R
C1
C2
Line Lock
9.1kΩ
6.8uF
0.68uF
18kΩ
3.4uF
0.34uF
Frame Lock
5.6MΩ
0.18uF
0.018uF
3.3MΩ
0.3uF
0.03uF
Rev.0
41
2002/01